ENGR00242572-1 pinctrl: imx: add imx6solo/duallite driver

The i.MX6Solo and i.MX6DualLite are using the same pads, so they share one
pinctrl driver and pad settings.
The IMX_MUX_MASK is changed to 0xf from 0x7 since the valid bits number of MUX
for i.MX6S/DL becomes 4 now.
It does not affect the exist i.MX6Q since that one more bit is not used
for i.MX6Q.

Reviewed-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>

1 files changed, 1693 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sdl-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sdl-pinctrl.txt
new file mode 100644
index 000000000000..b1169041326d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sdl-pinctrl.txt
@@ -0,0 +1,1693 @@
+* Freescale i.MX 6Solo/6DualLite IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6sdl-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin.
+  Please refer to imx6solo/imx6dl datasheet for the valid pad config settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS                     (1 << 16)
+PAD_CTL_PUS_100K_DOWN           (0 << 14)
+PAD_CTL_PUS_47K_UP              (1 << 14)
+PAD_CTL_PUS_100K_UP             (2 << 14)
+PAD_CTL_PUS_22K_UP              (3 << 14)
+PAD_CTL_PUE                     (1 << 13)
+PAD_CTL_PKE                     (1 << 12)
+PAD_CTL_ODE                     (1 << 11)
+PAD_CTL_SPEED_LOW               (1 << 6)
+PAD_CTL_SPEED_MED               (2 << 6)
+PAD_CTL_SPEED_HIGH              (3 << 6)
+PAD_CTL_DSE_DISABLE             (0 << 3)
+PAD_CTL_DSE_240ohm              (1 << 3)
+PAD_CTL_DSE_120ohm              (2 << 3)
+PAD_CTL_DSE_80ohm               (3 << 3)
+PAD_CTL_DSE_60ohm               (4 << 3)
+PAD_CTL_DSE_48ohm               (5 << 3)
+PAD_CTL_DSE_40ohm               (6 << 3)
+PAD_CTL_DSE_34ohm               (7 << 3)
+PAD_CTL_SRE_FAST                (1 << 0)
+PAD_CTL_SRE_SLOW                (0 << 0)
+
+See below for available PIN_FUNC_ID for imx6sdl:
+0	MX6SDL_PAD_CSI0_DAT10__IPU1_CSI0_D_10
+1	MX6SDL_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC
+2	MX6SDL_PAD_CSI0_DAT10__ECSPI2_MISO
+3	MX6SDL_PAD_CSI0_DAT10__UART1_TXD
+4	MX6SDL_PAD_CSI0_DAT10__UART1_RXD
+5	MX6SDL_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4
+6	MX6SDL_PAD_CSI0_DAT10__GPIO_5_28
+7	MX6SDL_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33
+8	MX6SDL_PAD_CSI0_DAT10__SIMBA_TRACE_7
+9	MX6SDL_PAD_CSI0_DAT11__IPU1_CSI0_D_11
+10	MX6SDL_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS
+11	MX6SDL_PAD_CSI0_DAT11__ECSPI2_SS0
+12	MX6SDL_PAD_CSI0_DAT11__UART1_TXD
+13	MX6SDL_PAD_CSI0_DAT11__UART1_RXD
+14	MX6SDL_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5
+15	MX6SDL_PAD_CSI0_DAT11__GPIO_5_29
+16	MX6SDL_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34
+17	MX6SDL_PAD_CSI0_DAT11__SIMBA_TRACE_8
+18	MX6SDL_PAD_CSI0_DAT12__IPU1_CSI0_D_12
+19	MX6SDL_PAD_CSI0_DAT12__WEIM_WEIM_D_8
+20	MX6SDL_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16
+21	MX6SDL_PAD_CSI0_DAT12__UART4_TXD
+22	MX6SDL_PAD_CSI0_DAT12__UART4_RXD
+23	MX6SDL_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6
+24	MX6SDL_PAD_CSI0_DAT12__GPIO_5_30
+25	MX6SDL_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35
+26	MX6SDL_PAD_CSI0_DAT12__SIMBA_TRACE_9
+27	MX6SDL_PAD_CSI0_DAT13__IPU1_CSI0_D_13
+28	MX6SDL_PAD_CSI0_DAT13__WEIM_WEIM_D_9
+29	MX6SDL_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17
+30	MX6SDL_PAD_CSI0_DAT13__UART4_TXD
+31	MX6SDL_PAD_CSI0_DAT13__UART4_RXD
+32	MX6SDL_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7
+33	MX6SDL_PAD_CSI0_DAT13__GPIO_5_31
+34	MX6SDL_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36
+35	MX6SDL_PAD_CSI0_DAT13__SIMBA_TRACE_10
+36	MX6SDL_PAD_CSI0_DAT14__IPU1_CSI0_D_14
+37	MX6SDL_PAD_CSI0_DAT14__WEIM_WEIM_D_10
+38	MX6SDL_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18
+39	MX6SDL_PAD_CSI0_DAT14__UART5_TXD
+40	MX6SDL_PAD_CSI0_DAT14__UART5_RXD
+41	MX6SDL_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8
+42	MX6SDL_PAD_CSI0_DAT14__GPIO_6_0
+43	MX6SDL_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37
+44	MX6SDL_PAD_CSI0_DAT14__SIMBA_TRACE_11
+45	MX6SDL_PAD_CSI0_DAT15__IPU1_CSI0_D_15
+46	MX6SDL_PAD_CSI0_DAT15__WEIM_WEIM_D_11
+47	MX6SDL_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19
+48	MX6SDL_PAD_CSI0_DAT15__UART5_TXD
+49	MX6SDL_PAD_CSI0_DAT15__UART5_RXD
+50	MX6SDL_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9
+51	MX6SDL_PAD_CSI0_DAT15__GPIO_6_1
+52	MX6SDL_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38
+53	MX6SDL_PAD_CSI0_DAT15__SIMBA_TRACE_12
+54	MX6SDL_PAD_CSI0_DAT16__IPU1_CSI0_D_16
+55	MX6SDL_PAD_CSI0_DAT16__WEIM_WEIM_D_12
+56	MX6SDL_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20
+57	MX6SDL_PAD_CSI0_DAT16__UART4_CTS
+58	MX6SDL_PAD_CSI0_DAT16__UART4_RTS
+59	MX6SDL_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10
+60	MX6SDL_PAD_CSI0_DAT16__GPIO_6_2
+61	MX6SDL_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39
+62	MX6SDL_PAD_CSI0_DAT16__SIMBA_TRACE_13
+63	MX6SDL_PAD_CSI0_DAT17__IPU1_CSI0_D_17
+64	MX6SDL_PAD_CSI0_DAT17__WEIM_WEIM_D_13
+65	MX6SDL_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21
+66	MX6SDL_PAD_CSI0_DAT17__UART4_CTS
+67	MX6SDL_PAD_CSI0_DAT17__UART4_RTS
+68	MX6SDL_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11
+69	MX6SDL_PAD_CSI0_DAT17__GPIO_6_3
+70	MX6SDL_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40
+71	MX6SDL_PAD_CSI0_DAT17__SIMBA_TRACE_14
+72	MX6SDL_PAD_CSI0_DAT18__IPU1_CSI0_D_18
+73	MX6SDL_PAD_CSI0_DAT18__WEIM_WEIM_D_14
+74	MX6SDL_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22
+75	MX6SDL_PAD_CSI0_DAT18__UART5_CTS
+76	MX6SDL_PAD_CSI0_DAT18__UART5_RTS
+77	MX6SDL_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12
+78	MX6SDL_PAD_CSI0_DAT18__GPIO_6_4
+79	MX6SDL_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41
+80	MX6SDL_PAD_CSI0_DAT18__SIMBA_TRACE_15
+81	MX6SDL_PAD_CSI0_DAT19__IPU1_CSI0_D_19
+82	MX6SDL_PAD_CSI0_DAT19__WEIM_WEIM_D_15
+83	MX6SDL_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23
+84	MX6SDL_PAD_CSI0_DAT19__UART5_CTS
+85	MX6SDL_PAD_CSI0_DAT19__UART5_RTS
+86	MX6SDL_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13
+87	MX6SDL_PAD_CSI0_DAT19__GPIO_6_5
+88	MX6SDL_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42
+89	MX6SDL_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9
+90	MX6SDL_PAD_CSI0_DAT4__IPU1_CSI0_D_4
+91	MX6SDL_PAD_CSI0_DAT4__WEIM_WEIM_D_2
+92	MX6SDL_PAD_CSI0_DAT4__ECSPI1_SCLK
+93	MX6SDL_PAD_CSI0_DAT4__KPP_COL_5
+94	MX6SDL_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC
+95	MX6SDL_PAD_CSI0_DAT4__GPIO_5_22
+96	MX6SDL_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43
+97	MX6SDL_PAD_CSI0_DAT4__SIMBA_TRACE_1
+98	MX6SDL_PAD_CSI0_DAT5__IPU1_CSI0_D_5
+99	MX6SDL_PAD_CSI0_DAT5__WEIM_WEIM_D_3
+100	MX6SDL_PAD_CSI0_DAT5__ECSPI1_MOSI
+101	MX6SDL_PAD_CSI0_DAT5__KPP_ROW_5
+102	MX6SDL_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD
+103	MX6SDL_PAD_CSI0_DAT5__GPIO_5_23
+104	MX6SDL_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44
+105	MX6SDL_PAD_CSI0_DAT5__SIMBA_TRACE_2
+106	MX6SDL_PAD_CSI0_DAT6__IPU1_CSI0_D_6
+107	MX6SDL_PAD_CSI0_DAT6__WEIM_WEIM_D_4
+108	MX6SDL_PAD_CSI0_DAT6__ECSPI1_MISO
+109	MX6SDL_PAD_CSI0_DAT6__KPP_COL_6
+110	MX6SDL_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS
+111	MX6SDL_PAD_CSI0_DAT6__GPIO_5_24
+112	MX6SDL_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45
+113	MX6SDL_PAD_CSI0_DAT6__SIMBA_TRACE_3
+114	MX6SDL_PAD_CSI0_DAT7__IPU1_CSI0_D_7
+115	MX6SDL_PAD_CSI0_DAT7__WEIM_WEIM_D_5
+116	MX6SDL_PAD_CSI0_DAT7__ECSPI1_SS0
+117	MX6SDL_PAD_CSI0_DAT7__KPP_ROW_6
+118	MX6SDL_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD
+119	MX6SDL_PAD_CSI0_DAT7__GPIO_5_25
+120	MX6SDL_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46
+121	MX6SDL_PAD_CSI0_DAT7__SIMBA_TRACE_4
+122	MX6SDL_PAD_CSI0_DAT8__IPU1_CSI0_D_8
+123	MX6SDL_PAD_CSI0_DAT8__WEIM_WEIM_D_6
+124	MX6SDL_PAD_CSI0_DAT8__ECSPI2_SCLK
+125	MX6SDL_PAD_CSI0_DAT8__KPP_COL_7
+126	MX6SDL_PAD_CSI0_DAT8__I2C1_SDA
+127	MX6SDL_PAD_CSI0_DAT8__GPIO_5_26
+128	MX6SDL_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47
+129	MX6SDL_PAD_CSI0_DAT8__SIMBA_TRACE_5
+130	MX6SDL_PAD_CSI0_DAT9__IPU1_CSI0_D_9
+131	MX6SDL_PAD_CSI0_DAT9__WEIM_WEIM_D_7
+132	MX6SDL_PAD_CSI0_DAT9__ECSPI2_MOSI
+133	MX6SDL_PAD_CSI0_DAT9__KPP_ROW_7
+134	MX6SDL_PAD_CSI0_DAT9__I2C1_SCL
+135	MX6SDL_PAD_CSI0_DAT9__GPIO_5_27
+136	MX6SDL_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48
+137	MX6SDL_PAD_CSI0_DAT9__SIMBA_TRACE_6
+138	MX6SDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN
+139	MX6SDL_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0
+140	MX6SDL_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14
+141	MX6SDL_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2
+142	MX6SDL_PAD_CSI0_DATA_EN__GPIO_5_20
+143	MX6SDL_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31
+144	MX6SDL_PAD_CSI0_DATA_EN__SIMBA_TRCLK
+145	MX6SDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC
+146	MX6SDL_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13
+147	MX6SDL_PAD_CSI0_MCLK__CCM_CLKO
+148	MX6SDL_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1
+149	MX6SDL_PAD_CSI0_MCLK__GPIO_5_19
+150	MX6SDL_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30
+151	MX6SDL_PAD_CSI0_MCLK__SIMBA_TRCTL
+152	MX6SDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK
+153	MX6SDL_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12
+154	MX6SDL_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0
+155	MX6SDL_PAD_CSI0_PIXCLK__GPIO_5_18
+156	MX6SDL_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29
+157	MX6SDL_PAD_CSI0_PIXCLK__SIMBA_EVENTO
+158	MX6SDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC
+159	MX6SDL_PAD_CSI0_VSYNC__WEIM_WEIM_D_1
+160	MX6SDL_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15
+161	MX6SDL_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3
+162	MX6SDL_PAD_CSI0_VSYNC__GPIO_5_21
+163	MX6SDL_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32
+164	MX6SDL_PAD_CSI0_VSYNC__SIMBA_TRACE_0
+165	MX6SDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
+166	MX6SDL_PAD_DI0_DISP_CLK__LCDIF_CLK
+167	MX6SDL_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28
+168	MX6SDL_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0
+169	MX6SDL_PAD_DI0_DISP_CLK__GPIO_4_16
+170	MX6SDL_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0
+171	MX6SDL_PAD_DI0_DISP_CLK__TPSMP_HDATA_DIR
+172	MX6SDL_PAD_DI0_DISP_CLK__LCDIF_WR_RWN
+173	MX6SDL_PAD_DI0_PIN15__IPU1_DI0_PIN15
+174	MX6SDL_PAD_DI0_PIN15__LCDIF_ENABLE
+175	MX6SDL_PAD_DI0_PIN15__AUDMUX_AUD6_TXC
+176	MX6SDL_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29
+177	MX6SDL_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1
+178	MX6SDL_PAD_DI0_PIN15__GPIO_4_17
+179	MX6SDL_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1
+180	MX6SDL_PAD_DI0_PIN15__PL301_SIM_MX6SDL_PER1_HSIZE_0
+181	MX6SDL_PAD_DI0_PIN15__LCDIF_RD_E
+182	MX6SDL_PAD_DI0_PIN2__IPU1_DI0_PIN2
+183	MX6SDL_PAD_DI0_PIN2__LCDIF_HSYNC
+184	MX6SDL_PAD_DI0_PIN2__AUDMUX_AUD6_TXD
+185	MX6SDL_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30
+186	MX6SDL_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2
+187	MX6SDL_PAD_DI0_PIN2__GPIO_4_18
+188	MX6SDL_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2
+189	MX6SDL_PAD_DI0_PIN2__PL301_SIM_MX6SDL_PER1_HADDR_9
+190	MX6SDL_PAD_DI0_PIN2__LCDIF_RS
+191	MX6SDL_PAD_DI0_PIN3__IPU1_DI0_PIN3
+192	MX6SDL_PAD_DI0_PIN3__LCDIF_VSYNC
+193	MX6SDL_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS
+194	MX6SDL_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31
+195	MX6SDL_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3
+196	MX6SDL_PAD_DI0_PIN3__GPIO_4_19
+197	MX6SDL_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3
+198	MX6SDL_PAD_DI0_PIN3__PL301_SIM_MX6SDL_PER1_HADDR_10
+199	MX6SDL_PAD_DI0_PIN3__LCDIF_CS
+200	MX6SDL_PAD_DI0_PIN4__IPU1_DI0_PIN4
+201	MX6SDL_PAD_DI0_PIN4__LCDIF_BUSY
+202	MX6SDL_PAD_DI0_PIN4__AUDMUX_AUD6_RXD
+203	MX6SDL_PAD_DI0_PIN4__USDHC1_WP
+204	MX6SDL_PAD_DI0_PIN4__SDMA_DEBUG_YIELD
+205	MX6SDL_PAD_DI0_PIN4__GPIO_4_20
+206	MX6SDL_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4
+207	MX6SDL_PAD_DI0_PIN4__PL301_SIM_MX6SDL_PER1_HADDR_11
+208	MX6SDL_PAD_DI0_PIN4__LCDIF_RESET
+209	MX6SDL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0
+210	MX6SDL_PAD_DISP0_DAT0__LCDIF_DAT_0
+211	MX6SDL_PAD_DISP0_DAT0__ECSPI3_SCLK
+212	MX6SDL_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0
+213	MX6SDL_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN
+214	MX6SDL_PAD_DISP0_DAT0__GPIO_4_21
+215	MX6SDL_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5
+216	MX6SDL_PAD_DISP0_DAT0__PL301_SIM_MX6SDL_PER1_HSIZE_1
+217	MX6SDL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1
+218	MX6SDL_PAD_DISP0_DAT1__LCDIF_DAT_1
+219	MX6SDL_PAD_DISP0_DAT1__ECSPI3_MOSI
+220	MX6SDL_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1
+221	MX6SDL_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+222	MX6SDL_PAD_DISP0_DAT1__GPIO_4_22
+223	MX6SDL_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6
+224	MX6SDL_PAD_DISP0_DAT1__PL301_SIM_MX6SDL_PER1_HADDR_12
+225	MX6SDL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10
+226	MX6SDL_PAD_DISP0_DAT10__LCDIF_DAT_10
+227	MX6SDL_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6
+228	MX6SDL_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+229	MX6SDL_PAD_DISP0_DAT10__GPIO_4_31
+230	MX6SDL_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15
+231	MX6SDL_PAD_DISP0_DAT10__PL301_SIM_MX6SDL_PER1_HADDR_21
+232	MX6SDL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11
+233	MX6SDL_PAD_DISP0_DAT11__LCDIF_DAT_11
+234	MX6SDL_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7
+235	MX6SDL_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+236	MX6SDL_PAD_DISP0_DAT11__GPIO_5_5
+237	MX6SDL_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16
+238	MX6SDL_PAD_DISP0_DAT11__PL301_SIM_MX6SDL_PER1_HADDR_22
+239	MX6SDL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12
+240	MX6SDL_PAD_DISP0_DAT12__LCDIF_DAT_12
+241	MX6SDL_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+242	MX6SDL_PAD_DISP0_DAT12__GPIO_5_6
+243	MX6SDL_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17
+244	MX6SDL_PAD_DISP0_DAT12__PL301_SIM_MX6SDL_PER1_HADDR_23
+245	MX6SDL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13
+246	MX6SDL_PAD_DISP0_DAT13__LCDIF_DAT_13
+247	MX6SDL_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS
+248	MX6SDL_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+249	MX6SDL_PAD_DISP0_DAT13__GPIO_5_7
+250	MX6SDL_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18
+251	MX6SDL_PAD_DISP0_DAT13__PL301_SIM_MX6SDL_PER1_HADDR_24
+252	MX6SDL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14
+253	MX6SDL_PAD_DISP0_DAT14__LCDIF_DAT_14
+254	MX6SDL_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC
+255	MX6SDL_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+256	MX6SDL_PAD_DISP0_DAT14__GPIO_5_8
+257	MX6SDL_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19
+258	MX6SDL_PAD_DISP0_DAT14__PL301_SIM_MX6SDL_PER1_HSIZE_2
+259	MX6SDL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15
+260	MX6SDL_PAD_DISP0_DAT15__LCDIF_DAT_15
+261	MX6SDL_PAD_DISP0_DAT15__ECSPI1_SS1
+262	MX6SDL_PAD_DISP0_DAT15__ECSPI2_SS1
+263	MX6SDL_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+264	MX6SDL_PAD_DISP0_DAT15__GPIO_5_9
+265	MX6SDL_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20
+266	MX6SDL_PAD_DISP0_DAT15__PL301_SIM_MX6SDL_PER1_HADDR_25
+267	MX6SDL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16
+268	MX6SDL_PAD_DISP0_DAT16__LCDIF_DAT_16
+269	MX6SDL_PAD_DISP0_DAT16__ECSPI2_MOSI
+270	MX6SDL_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC
+271	MX6SDL_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0
+272	MX6SDL_PAD_DISP0_DAT16__GPIO_5_10
+273	MX6SDL_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21
+274	MX6SDL_PAD_DISP0_DAT16__PL301_SIM_MX6SDL_PER1_HADDR_26
+275	MX6SDL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17
+276	MX6SDL_PAD_DISP0_DAT17__LCDIF_DAT_17
+277	MX6SDL_PAD_DISP0_DAT17__ECSPI2_MISO
+278	MX6SDL_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD
+279	MX6SDL_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1
+280	MX6SDL_PAD_DISP0_DAT17__GPIO_5_11
+281	MX6SDL_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22
+282	MX6SDL_PAD_DISP0_DAT17__PL301_SIM_MX6SDL_PER1_HADDR_27
+283	MX6SDL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18
+284	MX6SDL_PAD_DISP0_DAT18__LCDIF_DAT_18
+285	MX6SDL_PAD_DISP0_DAT18__ECSPI2_SS0
+286	MX6SDL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS
+287	MX6SDL_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS
+288	MX6SDL_PAD_DISP0_DAT18__GPIO_5_12
+289	MX6SDL_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23
+290	MX6SDL_PAD_DISP0_DAT18__WEIM_WEIM_CS_2
+291	MX6SDL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19
+292	MX6SDL_PAD_DISP0_DAT19__LCDIF_DAT_19
+293	MX6SDL_PAD_DISP0_DAT19__ECSPI2_SCLK
+294	MX6SDL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD
+295	MX6SDL_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC
+296	MX6SDL_PAD_DISP0_DAT19__GPIO_5_13
+297	MX6SDL_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24
+298	MX6SDL_PAD_DISP0_DAT19__WEIM_WEIM_CS_3
+299	MX6SDL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2
+300	MX6SDL_PAD_DISP0_DAT2__LCDIF_DAT_2
+301	MX6SDL_PAD_DISP0_DAT2__ECSPI3_MISO
+302	MX6SDL_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2
+303	MX6SDL_PAD_DISP0_DAT2__SDMA_DEBUG_MODE
+304	MX6SDL_PAD_DISP0_DAT2__GPIO_4_23
+305	MX6SDL_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7
+306	MX6SDL_PAD_DISP0_DAT2__PL301_SIM_MX6SDL_PER1_HADDR_13
+307	MX6SDL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20
+308	MX6SDL_PAD_DISP0_DAT20__LCDIF_DAT_20
+309	MX6SDL_PAD_DISP0_DAT20__ECSPI1_SCLK
+310	MX6SDL_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC
+311	MX6SDL_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+312	MX6SDL_PAD_DISP0_DAT20__GPIO_5_14
+313	MX6SDL_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25
+314	MX6SDL_PAD_DISP0_DAT20__PL301_SIM_MX6SDL_PER1_HADDR_28
+315	MX6SDL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21
+316	MX6SDL_PAD_DISP0_DAT21__LCDIF_DAT_21
+317	MX6SDL_PAD_DISP0_DAT21__ECSPI1_MOSI
+318	MX6SDL_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD
+319	MX6SDL_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0
+320	MX6SDL_PAD_DISP0_DAT21__GPIO_5_15
+321	MX6SDL_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26
+322	MX6SDL_PAD_DISP0_DAT21__PL301_SIM_MX6SDL_PER1_HADDR_29
+323	MX6SDL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22
+324	MX6SDL_PAD_DISP0_DAT22__LCDIF_DAT_22
+325	MX6SDL_PAD_DISP0_DAT22__ECSPI1_MISO
+326	MX6SDL_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS
+327	MX6SDL_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1
+328	MX6SDL_PAD_DISP0_DAT22__GPIO_5_16
+329	MX6SDL_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27
+330	MX6SDL_PAD_DISP0_DAT22__PL301_SIM_MX6SDL_PER1_HADDR_30
+331	MX6SDL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23
+332	MX6SDL_PAD_DISP0_DAT23__LCDIF_DAT_23
+333	MX6SDL_PAD_DISP0_DAT23__ECSPI1_SS0
+334	MX6SDL_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD
+335	MX6SDL_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2
+336	MX6SDL_PAD_DISP0_DAT23__GPIO_5_17
+337	MX6SDL_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28
+338	MX6SDL_PAD_DISP0_DAT23__PL301_SIM_MX6SDL_PER1_HADDR_31
+339	MX6SDL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3
+340	MX6SDL_PAD_DISP0_DAT3__LCDIF_DAT_3
+341	MX6SDL_PAD_DISP0_DAT3__ECSPI3_SS0
+342	MX6SDL_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3
+343	MX6SDL_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR
+344	MX6SDL_PAD_DISP0_DAT3__GPIO_4_24
+345	MX6SDL_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8
+346	MX6SDL_PAD_DISP0_DAT3__PL301_SIM_MX6SDL_PER1_HADDR_14
+347	MX6SDL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4
+348	MX6SDL_PAD_DISP0_DAT4__LCDIF_DAT_4
+349	MX6SDL_PAD_DISP0_DAT4__ECSPI3_SS1
+350	MX6SDL_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4
+351	MX6SDL_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB
+352	MX6SDL_PAD_DISP0_DAT4__GPIO_4_25
+353	MX6SDL_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9
+354	MX6SDL_PAD_DISP0_DAT4__PL301_SIM_MX6SDL_PER1_HADDR_15
+355	MX6SDL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5
+356	MX6SDL_PAD_DISP0_DAT5__LCDIF_DAT_5
+357	MX6SDL_PAD_DISP0_DAT5__ECSPI3_SS2
+358	MX6SDL_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS
+359	MX6SDL_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS
+360	MX6SDL_PAD_DISP0_DAT5__GPIO_4_26
+361	MX6SDL_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10
+362	MX6SDL_PAD_DISP0_DAT5__PL301_SIM_MX6SDL_PER1_HADDR_16
+363	MX6SDL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6
+364	MX6SDL_PAD_DISP0_DAT6__LCDIF_DAT_6
+365	MX6SDL_PAD_DISP0_DAT6__ECSPI3_SS3
+366	MX6SDL_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC
+367	MX6SDL_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE
+368	MX6SDL_PAD_DISP0_DAT6__GPIO_4_27
+369	MX6SDL_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11
+370	MX6SDL_PAD_DISP0_DAT6__PL301_SIM_MX6SDL_PER1_HADDR_17
+371	MX6SDL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7
+372	MX6SDL_PAD_DISP0_DAT7__LCDIF_DAT_7
+373	MX6SDL_PAD_DISP0_DAT7__ECSPI3_RDY
+374	MX6SDL_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5
+375	MX6SDL_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0
+376	MX6SDL_PAD_DISP0_DAT7__GPIO_4_28
+377	MX6SDL_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12
+378	MX6SDL_PAD_DISP0_DAT7__PL301_SIM_MX6SDL_PER1_HADDR_18
+379	MX6SDL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8
+380	MX6SDL_PAD_DISP0_DAT8__LCDIF_DAT_8
+381	MX6SDL_PAD_DISP0_DAT8__PWM1_PWMO
+382	MX6SDL_PAD_DISP0_DAT8__WDOG1_WDOG_B
+383	MX6SDL_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1
+384	MX6SDL_PAD_DISP0_DAT8__GPIO_4_29
+385	MX6SDL_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13
+386	MX6SDL_PAD_DISP0_DAT8__PL301_SIM_MX6SDL_PER1_HADDR_19
+387	MX6SDL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9
+388	MX6SDL_PAD_DISP0_DAT9__LCDIF_DAT_9
+389	MX6SDL_PAD_DISP0_DAT9__PWM2_PWMO
+390	MX6SDL_PAD_DISP0_DAT9__WDOG2_WDOG_B
+391	MX6SDL_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2
+392	MX6SDL_PAD_DISP0_DAT9__GPIO_4_30
+393	MX6SDL_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14
+394	MX6SDL_PAD_DISP0_DAT9__PL301_SIM_MX6SDL_PER1_HADDR_20
+395	MX6SDL_PAD_DRAM_A0__MMDC_DRAM_A_0
+396	MX6SDL_PAD_DRAM_A1__MMDC_DRAM_A_1
+397	MX6SDL_PAD_DRAM_A10__MMDC_DRAM_A_10
+398	MX6SDL_PAD_DRAM_A11__MMDC_DRAM_A_11
+399	MX6SDL_PAD_DRAM_A12__MMDC_DRAM_A_12
+400	MX6SDL_PAD_DRAM_A13__MMDC_DRAM_A_13
+401	MX6SDL_PAD_DRAM_A14__MMDC_DRAM_A_14
+402	MX6SDL_PAD_DRAM_A15__MMDC_DRAM_A_15
+403	MX6SDL_PAD_DRAM_A2__MMDC_DRAM_A_2
+404	MX6SDL_PAD_DRAM_A3__MMDC_DRAM_A_3
+405	MX6SDL_PAD_DRAM_A4__MMDC_DRAM_A_4
+406	MX6SDL_PAD_DRAM_A5__MMDC_DRAM_A_5
+407	MX6SDL_PAD_DRAM_A6__MMDC_DRAM_A_6
+408	MX6SDL_PAD_DRAM_A7__MMDC_DRAM_A_7
+409	MX6SDL_PAD_DRAM_A8__MMDC_DRAM_A_8
+410	MX6SDL_PAD_DRAM_A9__MMDC_DRAM_A_9
+411	MX6SDL_PAD_DRAM_CAS__MMDC_DRAM_CAS
+412	MX6SDL_PAD_DRAM_CS0__MMDC_DRAM_CS_0
+413	MX6SDL_PAD_DRAM_CS1__MMDC_DRAM_CS_1
+414	MX6SDL_PAD_DRAM_D0__MMDC_DRAM_D_0
+415	MX6SDL_PAD_DRAM_D1__MMDC_DRAM_D_1
+416	MX6SDL_PAD_DRAM_D10__MMDC_DRAM_D_10
+417	MX6SDL_PAD_DRAM_D11__MMDC_DRAM_D_11
+418	MX6SDL_PAD_DRAM_D12__MMDC_DRAM_D_12
+419	MX6SDL_PAD_DRAM_D13__MMDC_DRAM_D_13
+420	MX6SDL_PAD_DRAM_D14__MMDC_DRAM_D_14
+421	MX6SDL_PAD_DRAM_D15__MMDC_DRAM_D_15
+422	MX6SDL_PAD_DRAM_D16__MMDC_DRAM_D_16
+423	MX6SDL_PAD_DRAM_D17__MMDC_DRAM_D_17
+424	MX6SDL_PAD_DRAM_D18__MMDC_DRAM_D_18
+425	MX6SDL_PAD_DRAM_D19__MMDC_DRAM_D_19
+426	MX6SDL_PAD_DRAM_D2__MMDC_DRAM_D_2
+427	MX6SDL_PAD_DRAM_D20__MMDC_DRAM_D_20
+428	MX6SDL_PAD_DRAM_D21__MMDC_DRAM_D_21
+429	MX6SDL_PAD_DRAM_D22__MMDC_DRAM_D_22
+430	MX6SDL_PAD_DRAM_D23__MMDC_DRAM_D_23
+431	MX6SDL_PAD_DRAM_D24__MMDC_DRAM_D_24
+432	MX6SDL_PAD_DRAM_D25__MMDC_DRAM_D_25
+433	MX6SDL_PAD_DRAM_D26__MMDC_DRAM_D_26
+434	MX6SDL_PAD_DRAM_D27__MMDC_DRAM_D_27
+435	MX6SDL_PAD_DRAM_D28__MMDC_DRAM_D_28
+436	MX6SDL_PAD_DRAM_D29__MMDC_DRAM_D_29
+437	MX6SDL_PAD_DRAM_D3__MMDC_DRAM_D_3
+438	MX6SDL_PAD_DRAM_D30__MMDC_DRAM_D_30
+439	MX6SDL_PAD_DRAM_D31__MMDC_DRAM_D_31
+440	MX6SDL_PAD_DRAM_D32__MMDC_DRAM_D_32
+441	MX6SDL_PAD_DRAM_D33__MMDC_DRAM_D_33
+442	MX6SDL_PAD_DRAM_D34__MMDC_DRAM_D_34
+443	MX6SDL_PAD_DRAM_D35__MMDC_DRAM_D_35
+444	MX6SDL_PAD_DRAM_D36__MMDC_DRAM_D_36
+445	MX6SDL_PAD_DRAM_D37__MMDC_DRAM_D_37
+446	MX6SDL_PAD_DRAM_D38__MMDC_DRAM_D_38
+447	MX6SDL_PAD_DRAM_D39__MMDC_DRAM_D_39
+448	MX6SDL_PAD_DRAM_D4__MMDC_DRAM_D_4
+449	MX6SDL_PAD_DRAM_D40__MMDC_DRAM_D_40
+450	MX6SDL_PAD_DRAM_D41__MMDC_DRAM_D_41
+451	MX6SDL_PAD_DRAM_D42__MMDC_DRAM_D_42
+452	MX6SDL_PAD_DRAM_D43__MMDC_DRAM_D_43
+453	MX6SDL_PAD_DRAM_D44__MMDC_DRAM_D_44
+454	MX6SDL_PAD_DRAM_D45__MMDC_DRAM_D_45
+455	MX6SDL_PAD_DRAM_D46__MMDC_DRAM_D_46
+456	MX6SDL_PAD_DRAM_D47__MMDC_DRAM_D_47
+457	MX6SDL_PAD_DRAM_D48__MMDC_DRAM_D_48
+458	MX6SDL_PAD_DRAM_D49__MMDC_DRAM_D_49
+459	MX6SDL_PAD_DRAM_D5__MMDC_DRAM_D_5
+460	MX6SDL_PAD_DRAM_D50__MMDC_DRAM_D_50
+461	MX6SDL_PAD_DRAM_D51__MMDC_DRAM_D_51
+462	MX6SDL_PAD_DRAM_D52__MMDC_DRAM_D_52
+463	MX6SDL_PAD_DRAM_D53__MMDC_DRAM_D_53
+464	MX6SDL_PAD_DRAM_D54__MMDC_DRAM_D_54
+465	MX6SDL_PAD_DRAM_D55__MMDC_DRAM_D_55
+466	MX6SDL_PAD_DRAM_D56__MMDC_DRAM_D_56
+467	MX6SDL_PAD_DRAM_D57__MMDC_DRAM_D_57
+468	MX6SDL_PAD_DRAM_D58__MMDC_DRAM_D_58
+469	MX6SDL_PAD_DRAM_D59__MMDC_DRAM_D_59
+470	MX6SDL_PAD_DRAM_D6__MMDC_DRAM_D_6
+471	MX6SDL_PAD_DRAM_D60__MMDC_DRAM_D_60
+472	MX6SDL_PAD_DRAM_D61__MMDC_DRAM_D_61
+473	MX6SDL_PAD_DRAM_D62__MMDC_DRAM_D_62
+474	MX6SDL_PAD_DRAM_D63__MMDC_DRAM_D_63
+475	MX6SDL_PAD_DRAM_D7__MMDC_DRAM_D_7
+476	MX6SDL_PAD_DRAM_D8__MMDC_DRAM_D_8
+477	MX6SDL_PAD_DRAM_D9__MMDC_DRAM_D_9
+478	MX6SDL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0
+479	MX6SDL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1
+480	MX6SDL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2
+481	MX6SDL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3
+482	MX6SDL_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4
+483	MX6SDL_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5
+484	MX6SDL_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6
+485	MX6SDL_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7
+486	MX6SDL_PAD_DRAM_RAS__MMDC_DRAM_RAS
+487	MX6SDL_PAD_DRAM_RESET__MMDC_DRAM_RESET
+488	MX6SDL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0
+489	MX6SDL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1
+490	MX6SDL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2
+491	MX6SDL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0
+492	MX6SDL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1
+493	MX6SDL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0
+494	MX6SDL_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1
+495	MX6SDL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0
+496	MX6SDL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1
+497	MX6SDL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0
+498	MX6SDL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1
+499	MX6SDL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2
+500	MX6SDL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3
+501	MX6SDL_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4
+502	MX6SDL_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5
+503	MX6SDL_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6
+504	MX6SDL_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7
+505	MX6SDL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE
+506	MX6SDL_PAD_EIM_A16__WEIM_WEIM_A_16
+507	MX6SDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK
+508	MX6SDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK
+509	MX6SDL_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23
+510	MX6SDL_PAD_EIM_A16__GPIO_2_22
+511	MX6SDL_PAD_EIM_A16__TPSMP_HDATA_6
+512	MX6SDL_PAD_EIM_A16__SRC_BT_CFG_16
+513	MX6SDL_PAD_EIM_A16__EPDC_SDDO_0
+514	MX6SDL_PAD_EIM_A17__WEIM_WEIM_A_17
+515	MX6SDL_PAD_EIM_A17__IPU1_DISP1_DAT_12
+516	MX6SDL_PAD_EIM_A17__IPU1_CSI1_D_12
+517	MX6SDL_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22
+518	MX6SDL_PAD_EIM_A17__GPIO_2_21
+519	MX6SDL_PAD_EIM_A17__TPSMP_HDATA_5
+520	MX6SDL_PAD_EIM_A17__SRC_BT_CFG_17
+521	MX6SDL_PAD_EIM_A17__EPDC_PWRSTAT
+522	MX6SDL_PAD_EIM_A18__WEIM_WEIM_A_18
+523	MX6SDL_PAD_EIM_A18__IPU1_DISP1_DAT_13
+524	MX6SDL_PAD_EIM_A18__IPU1_CSI1_D_13
+525	MX6SDL_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21
+526	MX6SDL_PAD_EIM_A18__GPIO_2_20
+527	MX6SDL_PAD_EIM_A18__TPSMP_HDATA_4
+528	MX6SDL_PAD_EIM_A18__SRC_BT_CFG_18
+529	MX6SDL_PAD_EIM_A18__EPDC_PWRCTRL_0
+530	MX6SDL_PAD_EIM_A19__WEIM_WEIM_A_19
+531	MX6SDL_PAD_EIM_A19__IPU1_DISP1_DAT_14
+532	MX6SDL_PAD_EIM_A19__IPU1_CSI1_D_14
+533	MX6SDL_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20
+534	MX6SDL_PAD_EIM_A19__GPIO_2_19
+535	MX6SDL_PAD_EIM_A19__TPSMP_HDATA_3
+536	MX6SDL_PAD_EIM_A19__SRC_BT_CFG_19
+537	MX6SDL_PAD_EIM_A19__EPDC_PWRCTRL_1
+538	MX6SDL_PAD_EIM_A20__WEIM_WEIM_A_20
+539	MX6SDL_PAD_EIM_A20__IPU1_DISP1_DAT_15
+540	MX6SDL_PAD_EIM_A20__IPU1_CSI1_D_15
+541	MX6SDL_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19
+542	MX6SDL_PAD_EIM_A20__GPIO_2_18
+543	MX6SDL_PAD_EIM_A20__TPSMP_HDATA_2
+544	MX6SDL_PAD_EIM_A20__SRC_BT_CFG_20
+545	MX6SDL_PAD_EIM_A20__EPDC_PWRCTRL_2
+546	MX6SDL_PAD_EIM_A21__WEIM_WEIM_A_21
+547	MX6SDL_PAD_EIM_A21__IPU1_DISP1_DAT_16
+548	MX6SDL_PAD_EIM_A21__IPU1_CSI1_D_16
+549	MX6SDL_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18
+550	MX6SDL_PAD_EIM_A21__GPIO_2_17
+551	MX6SDL_PAD_EIM_A21__TPSMP_HDATA_1
+552	MX6SDL_PAD_EIM_A21__SRC_BT_CFG_21
+553	MX6SDL_PAD_EIM_A21__EPDC_GDCLK
+554	MX6SDL_PAD_EIM_A22__WEIM_WEIM_A_22
+555	MX6SDL_PAD_EIM_A22__IPU1_DISP1_DAT_17
+556	MX6SDL_PAD_EIM_A22__IPU1_CSI1_D_17
+557	MX6SDL_PAD_EIM_A22__GPIO_2_16
+558	MX6SDL_PAD_EIM_A22__TPSMP_HDATA_0
+559	MX6SDL_PAD_EIM_A22__SRC_BT_CFG_22
+560	MX6SDL_PAD_EIM_A22__EPDC_GDSP
+561	MX6SDL_PAD_EIM_A23__WEIM_WEIM_A_23
+562	MX6SDL_PAD_EIM_A23__IPU1_DISP1_DAT_18
+563	MX6SDL_PAD_EIM_A23__IPU1_CSI1_D_18
+564	MX6SDL_PAD_EIM_A23__IPU1_SISG_3
+565	MX6SDL_PAD_EIM_A23__GPIO_6_6
+566	MX6SDL_PAD_EIM_A23__PL301_SIM_MX6SDL_PER1_HPROT_3
+567	MX6SDL_PAD_EIM_A23__SRC_BT_CFG_23
+568	MX6SDL_PAD_EIM_A23__EPDC_GDOE
+569	MX6SDL_PAD_EIM_A24__WEIM_WEIM_A_24
+570	MX6SDL_PAD_EIM_A24__IPU1_DISP1_DAT_19
+571	MX6SDL_PAD_EIM_A24__IPU1_CSI1_D_19
+572	MX6SDL_PAD_EIM_A24__IPU1_SISG_2
+573	MX6SDL_PAD_EIM_A24__GPIO_5_4
+574	MX6SDL_PAD_EIM_A24__PL301_SIM_MX6SDL_PER1_HPROT_2
+575	MX6SDL_PAD_EIM_A24__SRC_BT_CFG_24
+576	MX6SDL_PAD_EIM_A24__EPDC_GDRL
+577	MX6SDL_PAD_EIM_A25__WEIM_WEIM_A_25
+578	MX6SDL_PAD_EIM_A25__ECSPI4_SS1
+579	MX6SDL_PAD_EIM_A25__ECSPI2_RDY
+580	MX6SDL_PAD_EIM_A25__IPU1_DI1_PIN12
+581	MX6SDL_PAD_EIM_A25__IPU1_DI0_D1_CS
+582	MX6SDL_PAD_EIM_A25__GPIO_5_2
+583	MX6SDL_PAD_EIM_A25__HDMI_TX_CEC_LINE
+584	MX6SDL_PAD_EIM_A25__PL301_SIM_MX6SDL_PER1_HBURST_0
+585	MX6SDL_PAD_EIM_A25__EPDC_SDDO_15
+586	MX6SDL_PAD_EIM_A25__WEIM_ACLK_FREERUN
+587	MX6SDL_PAD_EIM_BCLK__WEIM_WEIM_BCLK
+588	MX6SDL_PAD_EIM_BCLK__IPU1_DI1_PIN16
+589	MX6SDL_PAD_EIM_BCLK__GPIO_6_31
+590	MX6SDL_PAD_EIM_BCLK__TPSMP_HDATA_31
+591	MX6SDL_PAD_EIM_BCLK__EPDC_SDCE_9
+592	MX6SDL_PAD_EIM_CS0__WEIM_WEIM_CS_0
+593	MX6SDL_PAD_EIM_CS0__IPU1_DI1_PIN5
+594	MX6SDL_PAD_EIM_CS0__ECSPI2_SCLK
+595	MX6SDL_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24
+596	MX6SDL_PAD_EIM_CS0__GPIO_2_23
+597	MX6SDL_PAD_EIM_CS0__TPSMP_HDATA_7
+598	MX6SDL_PAD_EIM_CS0__EPDC_SDDO_6
+599	MX6SDL_PAD_EIM_CS1__WEIM_WEIM_CS_1
+600	MX6SDL_PAD_EIM_CS1__IPU1_DI1_PIN6
+601	MX6SDL_PAD_EIM_CS1__ECSPI2_MOSI
+602	MX6SDL_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25
+603	MX6SDL_PAD_EIM_CS1__GPIO_2_24
+604	MX6SDL_PAD_EIM_CS1__TPSMP_HDATA_8
+605	MX6SDL_PAD_EIM_CS1__EPDC_SDDO_8
+606	MX6SDL_PAD_EIM_D16__WEIM_WEIM_D_16
+607	MX6SDL_PAD_EIM_D16__ECSPI1_SCLK
+608	MX6SDL_PAD_EIM_D16__IPU1_DI0_PIN5
+609	MX6SDL_PAD_EIM_D16__IPU1_CSI1_D_18
+610	MX6SDL_PAD_EIM_D16__HDMI_TX_DDC_SDA
+611	MX6SDL_PAD_EIM_D16__GPIO_3_16
+612	MX6SDL_PAD_EIM_D16__I2C2_SDA
+613	MX6SDL_PAD_EIM_D16__TPSMP_HTRANS_0
+614	MX6SDL_PAD_EIM_D16__EPDC_SDDO_10
+615	MX6SDL_PAD_EIM_D17__WEIM_WEIM_D_17
+616	MX6SDL_PAD_EIM_D17__ECSPI1_MISO
+617	MX6SDL_PAD_EIM_D17__IPU1_DI0_PIN6
+618	MX6SDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK
+619	MX6SDL_PAD_EIM_D17__DCIC1_DCIC_OUT
+620	MX6SDL_PAD_EIM_D17__GPIO_3_17
+621	MX6SDL_PAD_EIM_D17__I2C3_SCL
+622	MX6SDL_PAD_EIM_D17__PL301_SIM_MX6SDL_PER1_HBURST_1
+623	MX6SDL_PAD_EIM_D17__EPDC_VCOM_0
+624	MX6SDL_PAD_EIM_D18__WEIM_WEIM_D_18
+625	MX6SDL_PAD_EIM_D18__ECSPI1_MOSI
+626	MX6SDL_PAD_EIM_D18__IPU1_DI0_PIN7
+627	MX6SDL_PAD_EIM_D18__IPU1_CSI1_D_17
+628	MX6SDL_PAD_EIM_D18__IPU1_DI1_D0_CS
+629	MX6SDL_PAD_EIM_D18__GPIO_3_18
+630	MX6SDL_PAD_EIM_D18__I2C3_SDA
+631	MX6SDL_PAD_EIM_D18__PL301_SIM_MX6SDL_PER1_HBURST_2
+632	MX6SDL_PAD_EIM_D18__EPDC_VCOM_1
+633	MX6SDL_PAD_EIM_D19__WEIM_WEIM_D_19
+634	MX6SDL_PAD_EIM_D19__ECSPI1_SS1
+635	MX6SDL_PAD_EIM_D19__IPU1_DI0_PIN8
+636	MX6SDL_PAD_EIM_D19__IPU1_CSI1_D_16
+637	MX6SDL_PAD_EIM_D19__UART1_CTS
+638	MX6SDL_PAD_EIM_D19__UART1_RTS
+639	MX6SDL_PAD_EIM_D19__GPIO_3_19
+640	MX6SDL_PAD_EIM_D19__EPIT1_EPITO
+641	MX6SDL_PAD_EIM_D19__PL301_SIM_MX6SDL_PER1_HRESP
+642	MX6SDL_PAD_EIM_D19__EPDC_SDDO_12
+643	MX6SDL_PAD_EIM_D20__WEIM_WEIM_D_20
+644	MX6SDL_PAD_EIM_D20__ECSPI4_SS0
+645	MX6SDL_PAD_EIM_D20__IPU1_DI0_PIN16
+646	MX6SDL_PAD_EIM_D20__IPU1_CSI1_D_15
+647	MX6SDL_PAD_EIM_D20__UART1_CTS
+648	MX6SDL_PAD_EIM_D20__UART1_RTS
+649	MX6SDL_PAD_EIM_D20__GPIO_3_20
+650	MX6SDL_PAD_EIM_D20__EPIT2_EPITO
+651	MX6SDL_PAD_EIM_D20__TPSMP_HTRANS_1
+652	MX6SDL_PAD_EIM_D21__WEIM_WEIM_D_21
+653	MX6SDL_PAD_EIM_D21__ECSPI4_SCLK
+654	MX6SDL_PAD_EIM_D21__IPU1_DI0_PIN17
+655	MX6SDL_PAD_EIM_D21__IPU1_CSI1_D_11
+656	MX6SDL_PAD_EIM_D21__USBOH3_USBOTG_OC
+657	MX6SDL_PAD_EIM_D21__GPIO_3_21
+658	MX6SDL_PAD_EIM_D21__I2C1_SCL
+659	MX6SDL_PAD_EIM_D21__SPDIF_IN1
+660	MX6SDL_PAD_EIM_D22__WEIM_WEIM_D_22
+661	MX6SDL_PAD_EIM_D22__ECSPI4_MISO
+662	MX6SDL_PAD_EIM_D22__IPU1_DI0_PIN1
+663	MX6SDL_PAD_EIM_D22__IPU1_CSI1_D_10
+664	MX6SDL_PAD_EIM_D22__USBOH3_USBOTG_PWR
+665	MX6SDL_PAD_EIM_D22__GPIO_3_22
+666	MX6SDL_PAD_EIM_D22__SPDIF_OUT1
+667	MX6SDL_PAD_EIM_D22__PL301_SIM_MX6SDL_PER1_HWRITE
+668	MX6SDL_PAD_EIM_D22__EPDC_SDCE_6
+669	MX6SDL_PAD_EIM_D23__WEIM_WEIM_D_23
+670	MX6SDL_PAD_EIM_D23__IPU1_DI0_D0_CS
+671	MX6SDL_PAD_EIM_D23__UART3_CTS
+672	MX6SDL_PAD_EIM_D23__UART3_RTS
+673	MX6SDL_PAD_EIM_D23__UART1_DCD
+674	MX6SDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN
+675	MX6SDL_PAD_EIM_D23__GPIO_3_23
+676	MX6SDL_PAD_EIM_D23__IPU1_DI1_PIN2
+677	MX6SDL_PAD_EIM_D23__IPU1_DI1_PIN14
+678	MX6SDL_PAD_EIM_D23__EPDC_SDDO_11
+679	MX6SDL_PAD_EIM_D24__WEIM_WEIM_D_24
+680	MX6SDL_PAD_EIM_D24__ECSPI4_SS2
+681	MX6SDL_PAD_EIM_D24__UART3_TXD
+682	MX6SDL_PAD_EIM_D24__UART3_RXD
+683	MX6SDL_PAD_EIM_D24__ECSPI1_SS2
+684	MX6SDL_PAD_EIM_D24__ECSPI2_SS2
+685	MX6SDL_PAD_EIM_D24__GPIO_3_24
+686	MX6SDL_PAD_EIM_D24__AUDMUX_AUD5_RXFS
+687	MX6SDL_PAD_EIM_D24__UART1_DTR
+688	MX6SDL_PAD_EIM_D24__EPDC_SDCE_7
+689	MX6SDL_PAD_EIM_D25__WEIM_WEIM_D_25
+690	MX6SDL_PAD_EIM_D25__ECSPI4_SS3
+691	MX6SDL_PAD_EIM_D25__UART3_TXD
+692	MX6SDL_PAD_EIM_D25__UART3_RXD
+693	MX6SDL_PAD_EIM_D25__ECSPI1_SS3
+694	MX6SDL_PAD_EIM_D25__ECSPI2_SS3
+695	MX6SDL_PAD_EIM_D25__GPIO_3_25
+696	MX6SDL_PAD_EIM_D25__AUDMUX_AUD5_RXC
+697	MX6SDL_PAD_EIM_D25__UART1_DSR
+698	MX6SDL_PAD_EIM_D25__EPDC_SDCE_8
+699	MX6SDL_PAD_EIM_D26__WEIM_WEIM_D_26
+700	MX6SDL_PAD_EIM_D26__IPU1_DI1_PIN11
+701	MX6SDL_PAD_EIM_D26__IPU1_CSI0_D_1
+702	MX6SDL_PAD_EIM_D26__IPU1_CSI1_D_14
+703	MX6SDL_PAD_EIM_D26__UART2_TXD
+704	MX6SDL_PAD_EIM_D26__UART2_RXD
+705	MX6SDL_PAD_EIM_D26__GPIO_3_26
+706	MX6SDL_PAD_EIM_D26__IPU1_SISG_2
+707	MX6SDL_PAD_EIM_D26__IPU1_DISP1_DAT_22
+708	MX6SDL_PAD_EIM_D26__EPDC_SDOED
+709	MX6SDL_PAD_EIM_D27__WEIM_WEIM_D_27
+710	MX6SDL_PAD_EIM_D27__IPU1_DI1_PIN13
+711	MX6SDL_PAD_EIM_D27__IPU1_CSI0_D_0
+712	MX6SDL_PAD_EIM_D27__IPU1_CSI1_D_13
+713	MX6SDL_PAD_EIM_D27__UART2_TXD
+714	MX6SDL_PAD_EIM_D27__UART2_RXD
+715	MX6SDL_PAD_EIM_D27__GPIO_3_27
+716	MX6SDL_PAD_EIM_D27__IPU1_SISG_3
+717	MX6SDL_PAD_EIM_D27__IPU1_DISP1_DAT_23
+718	MX6SDL_PAD_EIM_D27__EPDC_SDOE
+719	MX6SDL_PAD_EIM_D28__WEIM_WEIM_D_28
+720	MX6SDL_PAD_EIM_D28__I2C1_SDA
+721	MX6SDL_PAD_EIM_D28__ECSPI4_MOSI
+722	MX6SDL_PAD_EIM_D28__IPU1_CSI1_D_12
+723	MX6SDL_PAD_EIM_D28__UART2_CTS
+724	MX6SDL_PAD_EIM_D28__UART2_RTS
+725	MX6SDL_PAD_EIM_D28__GPIO_3_28
+726	MX6SDL_PAD_EIM_D28__IPU1_EXT_TRIG
+727	MX6SDL_PAD_EIM_D28__IPU1_DI0_PIN13
+728	MX6SDL_PAD_EIM_D28__EPDC_PWRCTRL_3
+729	MX6SDL_PAD_EIM_D29__WEIM_WEIM_D_29
+730	MX6SDL_PAD_EIM_D29__IPU1_DI1_PIN15
+731	MX6SDL_PAD_EIM_D29__ECSPI4_SS0
+732	MX6SDL_PAD_EIM_D29__UART2_CTS
+733	MX6SDL_PAD_EIM_D29__UART2_RTS
+734	MX6SDL_PAD_EIM_D29__GPIO_3_29
+735	MX6SDL_PAD_EIM_D29__IPU1_CSI1_VSYNC
+736	MX6SDL_PAD_EIM_D29__IPU1_DI0_PIN14
+737	MX6SDL_PAD_EIM_D29__EPDC_PWRWAKE
+738	MX6SDL_PAD_EIM_D30__WEIM_WEIM_D_30
+739	MX6SDL_PAD_EIM_D30__IPU1_DISP1_DAT_21
+740	MX6SDL_PAD_EIM_D30__IPU1_DI0_PIN11
+741	MX6SDL_PAD_EIM_D30__IPU1_CSI0_D_3
+742	MX6SDL_PAD_EIM_D30__UART3_CTS
+743	MX6SDL_PAD_EIM_D30__UART3_RTS
+744	MX6SDL_PAD_EIM_D30__GPIO_3_30
+745	MX6SDL_PAD_EIM_D30__USBOH3_USBH1_OC
+746	MX6SDL_PAD_EIM_D30__PL301_SIM_MX6SDL_PER1_HPROT_0
+747	MX6SDL_PAD_EIM_D30__EPDC_SDOEZ
+748	MX6SDL_PAD_EIM_D31__WEIM_WEIM_D_31
+749	MX6SDL_PAD_EIM_D31__IPU1_DISP1_DAT_20
+750	MX6SDL_PAD_EIM_D31__IPU1_DI0_PIN12
+751	MX6SDL_PAD_EIM_D31__IPU1_CSI0_D_2
+752	MX6SDL_PAD_EIM_D31__UART3_CTS
+753	MX6SDL_PAD_EIM_D31__UART3_RTS
+754	MX6SDL_PAD_EIM_D31__GPIO_3_31
+755	MX6SDL_PAD_EIM_D31__USBOH3_USBH1_PWR
+756	MX6SDL_PAD_EIM_D31__PL301_SIM_MX6SDL_PER1_HPROT_1
+757	MX6SDL_PAD_EIM_D31__EPDC_SDCLK
+758	MX6SDL_PAD_EIM_D31__WEIM_ACLK_FREERUN
+759	MX6SDL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0
+760	MX6SDL_PAD_EIM_DA0__IPU1_DISP1_DAT_9
+761	MX6SDL_PAD_EIM_DA0__IPU1_CSI1_D_9
+762	MX6SDL_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2
+763	MX6SDL_PAD_EIM_DA0__GPIO_3_0
+764	MX6SDL_PAD_EIM_DA0__TPSMP_HDATA_14
+765	MX6SDL_PAD_EIM_DA0__SRC_BT_CFG_0
+766	MX6SDL_PAD_EIM_DA0__EPDC_SDCLKN
+767	MX6SDL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1
+768	MX6SDL_PAD_EIM_DA1__IPU1_DISP1_DAT_8
+769	MX6SDL_PAD_EIM_DA1__IPU1_CSI1_D_8
+770	MX6SDL_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3
+771	MX6SDL_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE
+772	MX6SDL_PAD_EIM_DA1__GPIO_3_1
+773	MX6SDL_PAD_EIM_DA1__TPSMP_HDATA_15
+774	MX6SDL_PAD_EIM_DA1__SRC_BT_CFG_1
+775	MX6SDL_PAD_EIM_DA1__EPDC_SDLE
+776	MX6SDL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10
+777	MX6SDL_PAD_EIM_DA10__IPU1_DI1_PIN15
+778	MX6SDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN
+779	MX6SDL_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12
+780	MX6SDL_PAD_EIM_DA10__GPIO_3_10
+781	MX6SDL_PAD_EIM_DA10__TPSMP_HDATA_24
+782	MX6SDL_PAD_EIM_DA10__SRC_BT_CFG_10
+783	MX6SDL_PAD_EIM_DA10__EPDC_SDDO_1
+784	MX6SDL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11
+785	MX6SDL_PAD_EIM_DA11__IPU1_DI1_PIN2
+786	MX6SDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC
+787	MX6SDL_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13
+788	MX6SDL_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6
+789	MX6SDL_PAD_EIM_DA11__GPIO_3_11
+790	MX6SDL_PAD_EIM_DA11__TPSMP_HDATA_25
+791	MX6SDL_PAD_EIM_DA11__SRC_BT_CFG_11
+792	MX6SDL_PAD_EIM_DA11__EPDC_SDDO_3
+793	MX6SDL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12
+794	MX6SDL_PAD_EIM_DA12__IPU1_DI1_PIN3
+795	MX6SDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC
+796	MX6SDL_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14
+797	MX6SDL_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3
+798	MX6SDL_PAD_EIM_DA12__GPIO_3_12
+799	MX6SDL_PAD_EIM_DA12__TPSMP_HDATA_26
+800	MX6SDL_PAD_EIM_DA12__SRC_BT_CFG_12
+801	MX6SDL_PAD_EIM_DA12__EPDC_SDDO_2
+802	MX6SDL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13
+803	MX6SDL_PAD_EIM_DA13__IPU1_DI1_D0_CS
+804	MX6SDL_PAD_EIM_DA13__CCM_DI1_EXT_CLK
+805	MX6SDL_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15
+806	MX6SDL_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4
+807	MX6SDL_PAD_EIM_DA13__GPIO_3_13
+808	MX6SDL_PAD_EIM_DA13__TPSMP_HDATA_27
+809	MX6SDL_PAD_EIM_DA13__SRC_BT_CFG_13
+810	MX6SDL_PAD_EIM_DA13__EPDC_SDDO_13
+811	MX6SDL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14
+812	MX6SDL_PAD_EIM_DA14__IPU1_DI1_D1_CS
+813	MX6SDL_PAD_EIM_DA14__CCM_DI0_EXT_CLK
+814	MX6SDL_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16
+815	MX6SDL_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5
+816	MX6SDL_PAD_EIM_DA14__GPIO_3_14
+817	MX6SDL_PAD_EIM_DA14__TPSMP_HDATA_28
+818	MX6SDL_PAD_EIM_DA14__SRC_BT_CFG_14
+819	MX6SDL_PAD_EIM_DA14__EPDC_SDDO_14
+820	MX6SDL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15
+821	MX6SDL_PAD_EIM_DA15__IPU1_DI1_PIN1
+822	MX6SDL_PAD_EIM_DA15__IPU1_DI1_PIN4
+823	MX6SDL_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17
+824	MX6SDL_PAD_EIM_DA15__GPIO_3_15
+825	MX6SDL_PAD_EIM_DA15__TPSMP_HDATA_29
+826	MX6SDL_PAD_EIM_DA15__SRC_BT_CFG_15
+827	MX6SDL_PAD_EIM_DA15__EPDC_SDDO_9
+828	MX6SDL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2
+829	MX6SDL_PAD_EIM_DA2__IPU1_DISP1_DAT_7
+830	MX6SDL_PAD_EIM_DA2__IPU1_CSI1_D_7
+831	MX6SDL_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4
+832	MX6SDL_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE
+833	MX6SDL_PAD_EIM_DA2__GPIO_3_2
+834	MX6SDL_PAD_EIM_DA2__TPSMP_HDATA_16
+835	MX6SDL_PAD_EIM_DA2__SRC_BT_CFG_2
+836	MX6SDL_PAD_EIM_DA2__EPDC_BDR_0
+837	MX6SDL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3
+838	MX6SDL_PAD_EIM_DA3__IPU1_DISP1_DAT_6
+839	MX6SDL_PAD_EIM_DA3__IPU1_CSI1_D_6
+840	MX6SDL_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5
+841	MX6SDL_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ
+842	MX6SDL_PAD_EIM_DA3__GPIO_3_3
+843	MX6SDL_PAD_EIM_DA3__TPSMP_HDATA_17
+844	MX6SDL_PAD_EIM_DA3__SRC_BT_CFG_3
+845	MX6SDL_PAD_EIM_DA3__EPDC_BDR_1
+846	MX6SDL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4
+847	MX6SDL_PAD_EIM_DA4__IPU1_DISP1_DAT_5
+848	MX6SDL_PAD_EIM_DA4__IPU1_CSI1_D_5
+849	MX6SDL_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6
+850	MX6SDL_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN
+851	MX6SDL_PAD_EIM_DA4__GPIO_3_4
+852	MX6SDL_PAD_EIM_DA4__TPSMP_HDATA_18
+853	MX6SDL_PAD_EIM_DA4__SRC_BT_CFG_4
+854	MX6SDL_PAD_EIM_DA4__EPDC_SDCE_0
+855	MX6SDL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5
+856	MX6SDL_PAD_EIM_DA5__IPU1_DISP1_DAT_4
+857	MX6SDL_PAD_EIM_DA5__IPU1_CSI1_D_4
+858	MX6SDL_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7
+859	MX6SDL_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP
+860	MX6SDL_PAD_EIM_DA5__GPIO_3_5
+861	MX6SDL_PAD_EIM_DA5__TPSMP_HDATA_19
+862	MX6SDL_PAD_EIM_DA5__SRC_BT_CFG_5
+863	MX6SDL_PAD_EIM_DA5__EPDC_SDCE_1
+864	MX6SDL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6
+865	MX6SDL_PAD_EIM_DA6__IPU1_DISP1_DAT_3
+866	MX6SDL_PAD_EIM_DA6__IPU1_CSI1_D_3
+867	MX6SDL_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8
+868	MX6SDL_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN
+869	MX6SDL_PAD_EIM_DA6__GPIO_3_6
+870	MX6SDL_PAD_EIM_DA6__TPSMP_HDATA_20
+871	MX6SDL_PAD_EIM_DA6__SRC_BT_CFG_6
+872	MX6SDL_PAD_EIM_DA6__EPDC_SDCE_2
+873	MX6SDL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7
+874	MX6SDL_PAD_EIM_DA7__IPU1_DISP1_DAT_2
+875	MX6SDL_PAD_EIM_DA7__IPU1_CSI1_D_2
+876	MX6SDL_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9
+877	MX6SDL_PAD_EIM_DA7__GPIO_3_7
+878	MX6SDL_PAD_EIM_DA7__TPSMP_HDATA_21
+879	MX6SDL_PAD_EIM_DA7__SRC_BT_CFG_7
+880	MX6SDL_PAD_EIM_DA7__EPDC_SDCE_3
+881	MX6SDL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8
+882	MX6SDL_PAD_EIM_DA8__IPU1_DISP1_DAT_1
+883	MX6SDL_PAD_EIM_DA8__IPU1_CSI1_D_1
+884	MX6SDL_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10
+885	MX6SDL_PAD_EIM_DA8__GPIO_3_8
+886	MX6SDL_PAD_EIM_DA8__TPSMP_HDATA_22
+887	MX6SDL_PAD_EIM_DA8__SRC_BT_CFG_8
+888	MX6SDL_PAD_EIM_DA8__EPDC_SDCE_4
+889	MX6SDL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9
+890	MX6SDL_PAD_EIM_DA9__IPU1_DISP1_DAT_0
+891	MX6SDL_PAD_EIM_DA9__IPU1_CSI1_D_0
+892	MX6SDL_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11
+893	MX6SDL_PAD_EIM_DA9__GPIO_3_9
+894	MX6SDL_PAD_EIM_DA9__TPSMP_HDATA_23
+895	MX6SDL_PAD_EIM_DA9__SRC_BT_CFG_9
+896	MX6SDL_PAD_EIM_DA9__EPDC_SDCE_5
+897	MX6SDL_PAD_EIM_EB0__WEIM_WEIM_EB_0
+898	MX6SDL_PAD_EIM_EB0__IPU1_DISP1_DAT_11
+899	MX6SDL_PAD_EIM_EB0__IPU1_CSI1_D_11
+900	MX6SDL_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0
+901	MX6SDL_PAD_EIM_EB0__CCM_PMIC_RDY
+902	MX6SDL_PAD_EIM_EB0__GPIO_2_28
+903	MX6SDL_PAD_EIM_EB0__TPSMP_HDATA_12
+904	MX6SDL_PAD_EIM_EB0__SRC_BT_CFG_27
+905	MX6SDL_PAD_EIM_EB0__EPDC_PWRCOM
+906	MX6SDL_PAD_EIM_EB1__WEIM_WEIM_EB_1
+907	MX6SDL_PAD_EIM_EB1__IPU1_DISP1_DAT_10
+908	MX6SDL_PAD_EIM_EB1__IPU1_CSI1_D_10
+909	MX6SDL_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1
+910	MX6SDL_PAD_EIM_EB1__GPIO_2_29
+911	MX6SDL_PAD_EIM_EB1__TPSMP_HDATA_13
+912	MX6SDL_PAD_EIM_EB1__SRC_BT_CFG_28
+913	MX6SDL_PAD_EIM_EB1__EPDC_SDSHR
+914	MX6SDL_PAD_EIM_EB2__WEIM_WEIM_EB_2
+915	MX6SDL_PAD_EIM_EB2__ECSPI1_SS0
+916	MX6SDL_PAD_EIM_EB2__CCM_DI1_EXT_CLK
+917	MX6SDL_PAD_EIM_EB2__IPU1_CSI1_D_19
+918	MX6SDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL
+919	MX6SDL_PAD_EIM_EB2__GPIO_2_30
+920	MX6SDL_PAD_EIM_EB2__I2C2_SCL
+921	MX6SDL_PAD_EIM_EB2__SRC_BT_CFG_30
+922	MX6SDL_PAD_EIM_EB2__EPDC_SDDO_5
+923	MX6SDL_PAD_EIM_EB3__WEIM_WEIM_EB_3
+924	MX6SDL_PAD_EIM_EB3__ECSPI4_RDY
+925	MX6SDL_PAD_EIM_EB3__UART3_CTS
+926	MX6SDL_PAD_EIM_EB3__UART3_RTS
+927	MX6SDL_PAD_EIM_EB3__UART1_RI
+928	MX6SDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC
+929	MX6SDL_PAD_EIM_EB3__GPIO_2_31
+930	MX6SDL_PAD_EIM_EB3__IPU1_DI1_PIN3
+931	MX6SDL_PAD_EIM_EB3__SRC_BT_CFG_31
+932	MX6SDL_PAD_EIM_EB3__EPDC_SDCE_0
+933	MX6SDL_PAD_EIM_EB3__WEIM_ACLK_FREERUN
+934	MX6SDL_PAD_EIM_LBA__WEIM_WEIM_LBA
+935	MX6SDL_PAD_EIM_LBA__IPU1_DI1_PIN17
+936	MX6SDL_PAD_EIM_LBA__ECSPI2_SS1
+937	MX6SDL_PAD_EIM_LBA__GPIO_2_27
+938	MX6SDL_PAD_EIM_LBA__TPSMP_HDATA_11
+939	MX6SDL_PAD_EIM_LBA__SRC_BT_CFG_26
+940	MX6SDL_PAD_EIM_LBA__EPDC_SDDO_4
+941	MX6SDL_PAD_EIM_OE__WEIM_WEIM_OE
+942	MX6SDL_PAD_EIM_OE__IPU1_DI1_PIN7
+943	MX6SDL_PAD_EIM_OE__ECSPI2_MISO
+944	MX6SDL_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26
+945	MX6SDL_PAD_EIM_OE__GPIO_2_25
+946	MX6SDL_PAD_EIM_OE__TPSMP_HDATA_9
+947	MX6SDL_PAD_EIM_OE__EPDC_PWRIRQ
+948	MX6SDL_PAD_EIM_RW__WEIM_WEIM_RW
+949	MX6SDL_PAD_EIM_RW__IPU1_DI1_PIN8
+950	MX6SDL_PAD_EIM_RW__ECSPI2_SS0
+951	MX6SDL_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27
+952	MX6SDL_PAD_EIM_RW__GPIO_2_26
+953	MX6SDL_PAD_EIM_RW__TPSMP_HDATA_10
+954	MX6SDL_PAD_EIM_RW__SRC_BT_CFG_29
+955	MX6SDL_PAD_EIM_RW__EPDC_SDDO_7
+956	MX6SDL_PAD_EIM_WAIT__WEIM_WEIM_WAIT
+957	MX6SDL_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B
+958	MX6SDL_PAD_EIM_WAIT__GPIO_5_0
+959	MX6SDL_PAD_EIM_WAIT__TPSMP_HDATA_30
+960	MX6SDL_PAD_EIM_WAIT__SRC_BT_CFG_25
+961	MX6SDL_PAD_ENET_CRS_DV__ENET_RX_EN
+962	MX6SDL_PAD_ENET_CRS_DV__ESAI1_SCKT
+963	MX6SDL_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK
+964	MX6SDL_PAD_ENET_CRS_DV__GPIO_1_25
+965	MX6SDL_PAD_ENET_CRS_DV__PHY_TDO
+966	MX6SDL_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD
+967	MX6SDL_PAD_ENET_MDC__MLB_MLBDAT
+968	MX6SDL_PAD_ENET_MDC__ENET_MDC
+969	MX6SDL_PAD_ENET_MDC__ESAI1_TX5_RX0
+970	MX6SDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN
+971	MX6SDL_PAD_ENET_MDC__GPIO_1_31
+972	MX6SDL_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET
+973	MX6SDL_PAD_ENET_MDIO__ENET_MDIO
+974	MX6SDL_PAD_ENET_MDIO__ESAI1_SCKR
+975	MX6SDL_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3
+976	MX6SDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT
+977	MX6SDL_PAD_ENET_MDIO__GPIO_1_22
+978	MX6SDL_PAD_ENET_MDIO__SPDIF_PLOCK
+979	MX6SDL_PAD_ENET_REF_CLK__ENET_TX_CLK
+980	MX6SDL_PAD_ENET_REF_CLK__ESAI1_FSR
+981	MX6SDL_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4
+982	MX6SDL_PAD_ENET_REF_CLK__GPIO_1_23
+983	MX6SDL_PAD_ENET_REF_CLK__SPDIF_SRCLK
+984	MX6SDL_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH
+985	MX6SDL_PAD_ENET_RX_ER__ANATOP_USBOTG_ID
+986	MX6SDL_PAD_ENET_RX_ER__ENET_RX_ER
+987	MX6SDL_PAD_ENET_RX_ER__ESAI1_HCKR
+988	MX6SDL_PAD_ENET_RX_ER__SPDIF_IN1
+989	MX6SDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT
+990	MX6SDL_PAD_ENET_RX_ER__GPIO_1_24
+991	MX6SDL_PAD_ENET_RX_ER__PHY_TDI
+992	MX6SDL_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD
+993	MX6SDL_PAD_ENET_RXD0__OSC32K_32K_OUT
+994	MX6SDL_PAD_ENET_RXD0__ENET_RDATA_0
+995	MX6SDL_PAD_ENET_RXD0__ESAI1_HCKT
+996	MX6SDL_PAD_ENET_RXD0__SPDIF_OUT1
+997	MX6SDL_PAD_ENET_RXD0__GPIO_1_27
+998	MX6SDL_PAD_ENET_RXD0__PHY_TMS
+999	MX6SDL_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV
+1000	MX6SDL_PAD_ENET_RXD1__MLB_MLBSIG
+1001	MX6SDL_PAD_ENET_RXD1__ENET_RDATA_1
+1002	MX6SDL_PAD_ENET_RXD1__ESAI1_FST
+1003	MX6SDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT
+1004	MX6SDL_PAD_ENET_RXD1__GPIO_1_26
+1005	MX6SDL_PAD_ENET_RXD1__PHY_TCK
+1006	MX6SDL_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET
+1007	MX6SDL_PAD_ENET_TX_EN__ENET_TX_EN
+1008	MX6SDL_PAD_ENET_TX_EN__ESAI1_TX3_RX2
+1009	MX6SDL_PAD_ENET_TX_EN__GPIO_1_28
+1010	MX6SDL_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH
+1011	MX6SDL_PAD_ENET_TX_EN__I2C4_SCL
+1012	MX6SDL_PAD_ENET_TXD0__ENET_TDATA_0
+1013	MX6SDL_PAD_ENET_TXD0__ESAI1_TX4_RX1
+1014	MX6SDL_PAD_ENET_TXD0__GPIO_1_30
+1015	MX6SDL_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD
+1016	MX6SDL_PAD_ENET_TXD1__MLB_MLBCLK
+1017	MX6SDL_PAD_ENET_TXD1__ENET_TDATA_1
+1018	MX6SDL_PAD_ENET_TXD1__ESAI1_TX2_RX3
+1019	MX6SDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN
+1020	MX6SDL_PAD_ENET_TXD1__GPIO_1_29
+1021	MX6SDL_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD
+1022	MX6SDL_PAD_ENET_TXD1__I2C4_SDA
+1023	MX6SDL_PAD_GPIO_0__CCM_CLKO
+1024	MX6SDL_PAD_GPIO_0__KPP_COL_5
+1025	MX6SDL_PAD_GPIO_0__ASRC_ASRC_EXT_CLK
+1026	MX6SDL_PAD_GPIO_0__EPIT1_EPITO
+1027	MX6SDL_PAD_GPIO_0__GPIO_1_0
+1028	MX6SDL_PAD_GPIO_0__USBOH3_USBH1_PWR
+1029	MX6SDL_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5
+1030	MX6SDL_PAD_GPIO_1__ESAI1_SCKR
+1031	MX6SDL_PAD_GPIO_1__WDOG2_WDOG_B
+1032	MX6SDL_PAD_GPIO_1__KPP_ROW_5
+1033	MX6SDL_PAD_GPIO_1__USBOTG_ID
+1034	MX6SDL_PAD_GPIO_1__PWM2_PWMO
+1035	MX6SDL_PAD_GPIO_1__GPIO_1_1
+1036	MX6SDL_PAD_GPIO_1__USDHC1_CD
+1037	MX6SDL_PAD_GPIO_1__SRC_TESTER_ACK
+1038	MX6SDL_PAD_GPIO_16__ESAI1_TX3_RX2
+1039	MX6SDL_PAD_GPIO_16__ENET_1588_EVENT2_IN
+1040	MX6SDL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT
+1041	MX6SDL_PAD_GPIO_16__USDHC1_LCTL
+1042	MX6SDL_PAD_GPIO_16__SPDIF_IN1
+1043	MX6SDL_PAD_GPIO_16__GPIO_7_11
+1044	MX6SDL_PAD_GPIO_16__I2C3_SDA
+1045	MX6SDL_PAD_GPIO_16__SJC_DE_B
+1046	MX6SDL_PAD_GPIO_17__ESAI1_TX0
+1047	MX6SDL_PAD_GPIO_17__ENET_1588_EVENT3_IN
+1048	MX6SDL_PAD_GPIO_17__CCM_PMIC_RDY
+1049	MX6SDL_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0
+1050	MX6SDL_PAD_GPIO_17__SPDIF_OUT1
+1051	MX6SDL_PAD_GPIO_17__GPIO_7_12
+1052	MX6SDL_PAD_GPIO_17__SJC_JTAG_ACT
+1053	MX6SDL_PAD_GPIO_18__ESAI1_TX1
+1054	MX6SDL_PAD_GPIO_18__ENET_RX_CLK
+1055	MX6SDL_PAD_GPIO_18__USDHC3_VSELECT
+1056	MX6SDL_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1
+1057	MX6SDL_PAD_GPIO_18__ASRC_ASRC_EXT_CLK
+1058	MX6SDL_PAD_GPIO_18__GPIO_7_13
+1059	MX6SDL_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL
+1060	MX6SDL_PAD_GPIO_18__SRC_SYSTEM_RST
+1061	MX6SDL_PAD_GPIO_19__KPP_COL_5
+1062	MX6SDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT
+1063	MX6SDL_PAD_GPIO_19__SPDIF_OUT1
+1064	MX6SDL_PAD_GPIO_19__CCM_CLKO
+1065	MX6SDL_PAD_GPIO_19__ECSPI1_RDY
+1066	MX6SDL_PAD_GPIO_19__GPIO_4_5
+1067	MX6SDL_PAD_GPIO_19__ENET_TX_ER
+1068	MX6SDL_PAD_GPIO_19__SRC_INT_BOOT
+1069	MX6SDL_PAD_GPIO_2__ESAI1_FST
+1070	MX6SDL_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2
+1071	MX6SDL_PAD_GPIO_2__KPP_ROW_6
+1072	MX6SDL_PAD_GPIO_2__CCM_CCM_OUT_1
+1073	MX6SDL_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0
+1074	MX6SDL_PAD_GPIO_2__GPIO_1_2
+1075	MX6SDL_PAD_GPIO_2__USDHC2_WP
+1076	MX6SDL_PAD_GPIO_2__MLB_MLBDAT
+1077	MX6SDL_PAD_GPIO_3__ESAI1_HCKR
+1078	MX6SDL_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0
+1079	MX6SDL_PAD_GPIO_3__I2C3_SCL
+1080	MX6SDL_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT
+1081	MX6SDL_PAD_GPIO_3__CCM_CLKO2
+1082	MX6SDL_PAD_GPIO_3__GPIO_1_3
+1083	MX6SDL_PAD_GPIO_3__USBOH3_USBH1_OC
+1084	MX6SDL_PAD_GPIO_3__MLB_MLBCLK
+1085	MX6SDL_PAD_GPIO_4__ESAI1_HCKT
+1086	MX6SDL_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3
+1087	MX6SDL_PAD_GPIO_4__KPP_COL_7
+1088	MX6SDL_PAD_GPIO_4__CCM_CCM_OUT_2
+1089	MX6SDL_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1
+1090	MX6SDL_PAD_GPIO_4__GPIO_1_4
+1091	MX6SDL_PAD_GPIO_4__USDHC2_CD
+1092	MX6SDL_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED
+1093	MX6SDL_PAD_GPIO_5__ESAI1_TX2_RX3
+1094	MX6SDL_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4
+1095	MX6SDL_PAD_GPIO_5__KPP_ROW_7
+1096	MX6SDL_PAD_GPIO_5__CCM_CLKO
+1097	MX6SDL_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2
+1098	MX6SDL_PAD_GPIO_5__GPIO_1_5
+1099	MX6SDL_PAD_GPIO_5__I2C3_SCL
+1100	MX6SDL_PAD_GPIO_5__SIMBA_EVENTI
+1101	MX6SDL_PAD_GPIO_6__ESAI1_SCKT
+1102	MX6SDL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1
+1103	MX6SDL_PAD_GPIO_6__I2C3_SDA
+1104	MX6SDL_PAD_GPIO_6__CCM_CCM_OUT_0
+1105	MX6SDL_PAD_GPIO_6__CSU_CSU_INT_DEB
+1106	MX6SDL_PAD_GPIO_6__GPIO_1_6
+1107	MX6SDL_PAD_GPIO_6__USDHC2_LCTL
+1108	MX6SDL_PAD_GPIO_6__MLB_MLBSIG
+1109	MX6SDL_PAD_GPIO_7__ESAI1_TX4_RX1
+1110	MX6SDL_PAD_GPIO_7__EPIT1_EPITO
+1111	MX6SDL_PAD_GPIO_7__CAN1_TXCAN
+1112	MX6SDL_PAD_GPIO_7__UART2_TXD
+1113	MX6SDL_PAD_GPIO_7__UART2_RXD
+1114	MX6SDL_PAD_GPIO_7__GPIO_1_7
+1115	MX6SDL_PAD_GPIO_7__SPDIF_PLOCK
+1116	MX6SDL_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE
+1117	MX6SDL_PAD_GPIO_7__I2C4_SCL
+1118	MX6SDL_PAD_GPIO_8__ESAI1_TX5_RX0
+1119	MX6SDL_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT
+1120	MX6SDL_PAD_GPIO_8__EPIT2_EPITO
+1121	MX6SDL_PAD_GPIO_8__CAN1_RXCAN
+1122	MX6SDL_PAD_GPIO_8__UART2_TXD
+1123	MX6SDL_PAD_GPIO_8__UART2_RXD
+1124	MX6SDL_PAD_GPIO_8__GPIO_1_8
+1125	MX6SDL_PAD_GPIO_8__SPDIF_SRCLK
+1126	MX6SDL_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP
+1127	MX6SDL_PAD_GPIO_8__I2C4_SDA
+1128	MX6SDL_PAD_GPIO_9__ESAI1_FSR
+1129	MX6SDL_PAD_GPIO_9__WDOG1_WDOG_B
+1130	MX6SDL_PAD_GPIO_9__KPP_COL_6
+1131	MX6SDL_PAD_GPIO_9__CCM_REF_EN_B
+1132	MX6SDL_PAD_GPIO_9__PWM1_PWMO
+1133	MX6SDL_PAD_GPIO_9__GPIO_1_9
+1134	MX6SDL_PAD_GPIO_9__USDHC1_WP
+1135	MX6SDL_PAD_GPIO_9__SRC_EARLY_RST
+1136	MX6SDL_PAD_JTAG_MOD__SJC_MOD
+1137	MX6SDL_PAD_JTAG_TCK__SJC_TCK
+1138	MX6SDL_PAD_JTAG_TDI__SJC_TDI
+1139	MX6SDL_PAD_JTAG_TDO__SJC_TDO
+1140	MX6SDL_PAD_JTAG_TMS__SJC_TMS
+1141	MX6SDL_PAD_JTAG_TRSTB__SJC_TRSTB
+1142	MX6SDL_PAD_KEY_COL0__ECSPI1_SCLK
+1143	MX6SDL_PAD_KEY_COL0__ENET_RDATA_3
+1144	MX6SDL_PAD_KEY_COL0__AUDMUX_AUD5_TXC
+1145	MX6SDL_PAD_KEY_COL0__KPP_COL_0
+1146	MX6SDL_PAD_KEY_COL0__UART4_TXD
+1147	MX6SDL_PAD_KEY_COL0__UART4_RXD
+1148	MX6SDL_PAD_KEY_COL0__GPIO_4_6
+1149	MX6SDL_PAD_KEY_COL0__DCIC1_DCIC_OUT
+1150	MX6SDL_PAD_KEY_COL0__SRC_ANY_PU_RST
+1151	MX6SDL_PAD_KEY_COL1__ECSPI1_MISO
+1152	MX6SDL_PAD_KEY_COL1__ENET_MDIO
+1153	MX6SDL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS
+1154	MX6SDL_PAD_KEY_COL1__KPP_COL_1
+1155	MX6SDL_PAD_KEY_COL1__UART5_TXD
+1156	MX6SDL_PAD_KEY_COL1__UART5_RXD
+1157	MX6SDL_PAD_KEY_COL1__GPIO_4_8
+1158	MX6SDL_PAD_KEY_COL1__USDHC1_VSELECT
+1159	MX6SDL_PAD_KEY_COL1__PL301_SIM_MX6SDL_PER1_HADDR_1
+1160	MX6SDL_PAD_KEY_COL2__ECSPI1_SS1
+1161	MX6SDL_PAD_KEY_COL2__ENET_RDATA_2
+1162	MX6SDL_PAD_KEY_COL2__CAN1_TXCAN
+1163	MX6SDL_PAD_KEY_COL2__KPP_COL_2
+1164	MX6SDL_PAD_KEY_COL2__ENET_MDC
+1165	MX6SDL_PAD_KEY_COL2__GPIO_4_10
+1166	MX6SDL_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP
+1167	MX6SDL_PAD_KEY_COL2__PL301_SIM_MX6SDL_PER1_HADDR_3
+1168	MX6SDL_PAD_KEY_COL3__ECSPI1_SS3
+1169	MX6SDL_PAD_KEY_COL3__ENET_CRS
+1170	MX6SDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL
+1171	MX6SDL_PAD_KEY_COL3__KPP_COL_3
+1172	MX6SDL_PAD_KEY_COL3__I2C2_SCL
+1173	MX6SDL_PAD_KEY_COL3__GPIO_4_12
+1174	MX6SDL_PAD_KEY_COL3__SPDIF_IN1
+1175	MX6SDL_PAD_KEY_COL3__PL301_SIM_MX6SDL_PER1_HADDR_5
+1176	MX6SDL_PAD_KEY_COL4__CAN2_TXCAN
+1177	MX6SDL_PAD_KEY_COL4__IPU1_SISG_4
+1178	MX6SDL_PAD_KEY_COL4__USBOH3_USBOTG_OC
+1179	MX6SDL_PAD_KEY_COL4__KPP_COL_4
+1180	MX6SDL_PAD_KEY_COL4__UART5_CTS
+1181	MX6SDL_PAD_KEY_COL4__UART5_RTS
+1182	MX6SDL_PAD_KEY_COL4__GPIO_4_14
+1183	MX6SDL_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49
+1184	MX6SDL_PAD_KEY_COL4__PL301_SIM_MX6SDL_PER1_HADDR_7
+1185	MX6SDL_PAD_KEY_ROW0__ECSPI1_MOSI
+1186	MX6SDL_PAD_KEY_ROW0__ENET_TDATA_3
+1187	MX6SDL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD
+1188	MX6SDL_PAD_KEY_ROW0__KPP_ROW_0
+1189	MX6SDL_PAD_KEY_ROW0__UART4_TXD
+1190	MX6SDL_PAD_KEY_ROW0__UART4_RXD
+1191	MX6SDL_PAD_KEY_ROW0__GPIO_4_7
+1192	MX6SDL_PAD_KEY_ROW0__DCIC2_DCIC_OUT
+1193	MX6SDL_PAD_KEY_ROW0__PL301_SIM_MX6SDL_PER1_HADDR_0
+1194	MX6SDL_PAD_KEY_ROW1__ECSPI1_SS0
+1195	MX6SDL_PAD_KEY_ROW1__ENET_COL
+1196	MX6SDL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD
+1197	MX6SDL_PAD_KEY_ROW1__KPP_ROW_1
+1198	MX6SDL_PAD_KEY_ROW1__UART5_TXD
+1199	MX6SDL_PAD_KEY_ROW1__UART5_RXD
+1200	MX6SDL_PAD_KEY_ROW1__GPIO_4_9
+1201	MX6SDL_PAD_KEY_ROW1__USDHC2_VSELECT
+1202	MX6SDL_PAD_KEY_ROW1__PL301_SIM_MX6SDL_PER1_HADDR_2
+1203	MX6SDL_PAD_KEY_ROW2__ECSPI1_SS2
+1204	MX6SDL_PAD_KEY_ROW2__ENET_TDATA_2
+1205	MX6SDL_PAD_KEY_ROW2__CAN1_RXCAN
+1206	MX6SDL_PAD_KEY_ROW2__KPP_ROW_2
+1207	MX6SDL_PAD_KEY_ROW2__USDHC2_VSELECT
+1208	MX6SDL_PAD_KEY_ROW2__GPIO_4_11
+1209	MX6SDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE
+1210	MX6SDL_PAD_KEY_ROW2__PL301_SIM_MX6SDL_PER1_HADDR_4
+1211	MX6SDL_PAD_KEY_ROW3__OSC32K_32K_OUT
+1212	MX6SDL_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK
+1213	MX6SDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA
+1214	MX6SDL_PAD_KEY_ROW3__KPP_ROW_3
+1215	MX6SDL_PAD_KEY_ROW3__I2C2_SDA
+1216	MX6SDL_PAD_KEY_ROW3__GPIO_4_13
+1217	MX6SDL_PAD_KEY_ROW3__USDHC1_VSELECT
+1218	MX6SDL_PAD_KEY_ROW3__PL301_SIM_MX6SDL_PER1_HADDR_6
+1219	MX6SDL_PAD_KEY_ROW4__CAN2_RXCAN
+1220	MX6SDL_PAD_KEY_ROW4__IPU1_SISG_5
+1221	MX6SDL_PAD_KEY_ROW4__USBOH3_USBOTG_PWR
+1222	MX6SDL_PAD_KEY_ROW4__KPP_ROW_4
+1223	MX6SDL_PAD_KEY_ROW4__UART5_CTS
+1224	MX6SDL_PAD_KEY_ROW4__UART5_RTS
+1225	MX6SDL_PAD_KEY_ROW4__GPIO_4_15
+1226	MX6SDL_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50
+1227	MX6SDL_PAD_KEY_ROW4__PL301_SIM_MX6SDL_PER1_HADDR_8
+1228	MX6SDL_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK
+1229	MX6SDL_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0
+1230	MX6SDL_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1
+1231	MX6SDL_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2
+1232	MX6SDL_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3
+1233	MX6SDL_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK
+1234	MX6SDL_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0
+1235	MX6SDL_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1
+1236	MX6SDL_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2
+1237	MX6SDL_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3
+1238	MX6SDL_PAD_NANDF_ALE__RAWNAND_ALE
+1239	MX6SDL_PAD_NANDF_ALE__USDHC4_RST
+1240	MX6SDL_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0
+1241	MX6SDL_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12
+1242	MX6SDL_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12
+1243	MX6SDL_PAD_NANDF_ALE__GPIO_6_8
+1244	MX6SDL_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24
+1245	MX6SDL_PAD_NANDF_ALE__USDHC3_CLKI
+1246	MX6SDL_PAD_NANDF_CLE__RAWNAND_CLE
+1247	MX6SDL_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31
+1248	MX6SDL_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11
+1249	MX6SDL_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11
+1250	MX6SDL_PAD_NANDF_CLE__GPIO_6_7
+1251	MX6SDL_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23
+1252	MX6SDL_PAD_NANDF_CLE__USDHC3_CLKO
+1253	MX6SDL_PAD_NANDF_CS0__RAWNAND_CE0N
+1254	MX6SDL_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15
+1255	MX6SDL_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15
+1256	MX6SDL_PAD_NANDF_CS0__GPIO_6_11
+1257	MX6SDL_PAD_NANDF_CS0__USDHC1_CLKO
+1258	MX6SDL_PAD_NANDF_CS1__RAWNAND_CE1N
+1259	MX6SDL_PAD_NANDF_CS1__USDHC4_VSELECT
+1260	MX6SDL_PAD_NANDF_CS1__USDHC3_VSELECT
+1261	MX6SDL_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3
+1262	MX6SDL_PAD_NANDF_CS1__GPIO_6_14
+1263	MX6SDL_PAD_NANDF_CS1__PL301_SIM_MX6SDL_PER1_HREADYOUT
+1264	MX6SDL_PAD_NANDF_CS1__USDHC1_CLKI
+1265	MX6SDL_PAD_NANDF_CS2__RAWNAND_CE2N
+1266	MX6SDL_PAD_NANDF_CS2__IPU1_SISG_0
+1267	MX6SDL_PAD_NANDF_CS2__ESAI1_TX0
+1268	MX6SDL_PAD_NANDF_CS2__WEIM_WEIM_CRE
+1269	MX6SDL_PAD_NANDF_CS2__CCM_CLKO2
+1270	MX6SDL_PAD_NANDF_CS2__GPIO_6_15
+1271	MX6SDL_PAD_NANDF_CS2__USDHC2_CLKO
+1272	MX6SDL_PAD_NANDF_CS3__RAWNAND_CE3N
+1273	MX6SDL_PAD_NANDF_CS3__IPU1_SISG_1
+1274	MX6SDL_PAD_NANDF_CS3__ESAI1_TX1
+1275	MX6SDL_PAD_NANDF_CS3__WEIM_WEIM_A_26
+1276	MX6SDL_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4
+1277	MX6SDL_PAD_NANDF_CS3__GPIO_6_16
+1278	MX6SDL_PAD_NANDF_CS3__TPSMP_CLK
+1279	MX6SDL_PAD_NANDF_CS3__USDHC2_CLKI
+1280	MX6SDL_PAD_NANDF_CS3__I2C4_SDA
+1281	MX6SDL_PAD_NANDF_D0__RAWNAND_D0
+1282	MX6SDL_PAD_NANDF_D0__USDHC1_DAT4
+1283	MX6SDL_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0
+1284	MX6SDL_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16
+1285	MX6SDL_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16
+1286	MX6SDL_PAD_NANDF_D0__GPIO_2_0
+1287	MX6SDL_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0
+1288	MX6SDL_PAD_NANDF_D1__RAWNAND_D1
+1289	MX6SDL_PAD_NANDF_D1__USDHC1_DAT5
+1290	MX6SDL_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1
+1291	MX6SDL_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17
+1292	MX6SDL_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17
+1293	MX6SDL_PAD_NANDF_D1__GPIO_2_1
+1294	MX6SDL_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1
+1295	MX6SDL_PAD_NANDF_D2__RAWNAND_D2
+1296	MX6SDL_PAD_NANDF_D2__USDHC1_DAT6
+1297	MX6SDL_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2
+1298	MX6SDL_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18
+1299	MX6SDL_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18
+1300	MX6SDL_PAD_NANDF_D2__GPIO_2_2
+1301	MX6SDL_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2
+1302	MX6SDL_PAD_NANDF_D3__RAWNAND_D3
+1303	MX6SDL_PAD_NANDF_D3__USDHC1_DAT7
+1304	MX6SDL_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3
+1305	MX6SDL_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19
+1306	MX6SDL_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19
+1307	MX6SDL_PAD_NANDF_D3__GPIO_2_3
+1308	MX6SDL_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3
+1309	MX6SDL_PAD_NANDF_D4__RAWNAND_D4
+1310	MX6SDL_PAD_NANDF_D4__USDHC2_DAT4
+1311	MX6SDL_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4
+1312	MX6SDL_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20
+1313	MX6SDL_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20
+1314	MX6SDL_PAD_NANDF_D4__GPIO_2_4
+1315	MX6SDL_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4
+1316	MX6SDL_PAD_NANDF_D5__RAWNAND_D5
+1317	MX6SDL_PAD_NANDF_D5__USDHC2_DAT5
+1318	MX6SDL_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5
+1319	MX6SDL_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21
+1320	MX6SDL_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21
+1321	MX6SDL_PAD_NANDF_D5__GPIO_2_5
+1322	MX6SDL_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5
+1323	MX6SDL_PAD_NANDF_D6__RAWNAND_D6
+1324	MX6SDL_PAD_NANDF_D6__USDHC2_DAT6
+1325	MX6SDL_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6
+1326	MX6SDL_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22
+1327	MX6SDL_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22
+1328	MX6SDL_PAD_NANDF_D6__GPIO_2_6
+1329	MX6SDL_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6
+1330	MX6SDL_PAD_NANDF_D7__RAWNAND_D7
+1331	MX6SDL_PAD_NANDF_D7__USDHC2_DAT7
+1332	MX6SDL_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7
+1333	MX6SDL_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23
+1334	MX6SDL_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23
+1335	MX6SDL_PAD_NANDF_D7__GPIO_2_7
+1336	MX6SDL_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7
+1337	MX6SDL_PAD_NANDF_RB0__RAWNAND_READY0
+1338	MX6SDL_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2
+1339	MX6SDL_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14
+1340	MX6SDL_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14
+1341	MX6SDL_PAD_NANDF_RB0__GPIO_6_10
+1342	MX6SDL_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33
+1343	MX6SDL_PAD_NANDF_RB0__USDHC4_CLKI
+1344	MX6SDL_PAD_NANDF_WP_B__RAWNAND_RESETN
+1345	MX6SDL_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1
+1346	MX6SDL_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13
+1347	MX6SDL_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13
+1348	MX6SDL_PAD_NANDF_WP_B__GPIO_6_9
+1349	MX6SDL_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32
+1350	MX6SDL_PAD_NANDF_WP_B__USDHC4_CLKO
+1351	MX6SDL_PAD_NANDF_WP_B__I2C4_SCL
+1352	MX6SDL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM
+1353	MX6SDL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ
+1354	MX6SDL_PAD_POR_B__SRC_POR_B
+1355	MX6SDL_PAD_RESET_IN_B__SRC_RESET_B
+1356	MX6SDL_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY
+1357	MX6SDL_PAD_RGMII_RD0__ENET_RGMII_RD0
+1358	MX6SDL_PAD_RGMII_RD0__GPIO_6_25
+1359	MX6SDL_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6
+1360	MX6SDL_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG
+1361	MX6SDL_PAD_RGMII_RD1__ENET_RGMII_RD1
+1362	MX6SDL_PAD_RGMII_RD1__GPIO_6_27
+1363	MX6SDL_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8
+1364	MX6SDL_PAD_RGMII_RD1__SJC_FAIL
+1365	MX6SDL_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA
+1366	MX6SDL_PAD_RGMII_RD2__ENET_RGMII_RD2
+1367	MX6SDL_PAD_RGMII_RD2__GPIO_6_28
+1368	MX6SDL_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9
+1369	MX6SDL_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE
+1370	MX6SDL_PAD_RGMII_RD3__ENET_RGMII_RD3
+1371	MX6SDL_PAD_RGMII_RD3__GPIO_6_29
+1372	MX6SDL_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10
+1373	MX6SDL_PAD_RGMII_RX_CTL__USBOH3_H3_DATA
+1374	MX6SDL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL
+1375	MX6SDL_PAD_RGMII_RX_CTL__GPIO_6_24
+1376	MX6SDL_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5
+1377	MX6SDL_PAD_RGMII_RXC__USBOH3_H3_STROBE
+1378	MX6SDL_PAD_RGMII_RXC__USBOH3_H3_STROBE_START
+1379	MX6SDL_PAD_RGMII_RXC__ENET_RGMII_RXC
+1380	MX6SDL_PAD_RGMII_RXC__GPIO_6_30
+1381	MX6SDL_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11
+1382	MX6SDL_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY
+1383	MX6SDL_PAD_RGMII_TD0__ENET_RGMII_TD0
+1384	MX6SDL_PAD_RGMII_TD0__GPIO_6_20
+1385	MX6SDL_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1
+1386	MX6SDL_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG
+1387	MX6SDL_PAD_RGMII_TD1__ENET_RGMII_TD1
+1388	MX6SDL_PAD_RGMII_TD1__GPIO_6_21
+1389	MX6SDL_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2
+1390	MX6SDL_PAD_RGMII_TD1__CCM_PLL3_BYP
+1391	MX6SDL_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA
+1392	MX6SDL_PAD_RGMII_TD2__ENET_RGMII_TD2
+1393	MX6SDL_PAD_RGMII_TD2__GPIO_6_22
+1394	MX6SDL_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3
+1395	MX6SDL_PAD_RGMII_TD2__CCM_PLL2_BYP
+1396	MX6SDL_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE
+1397	MX6SDL_PAD_RGMII_TD3__ENET_RGMII_TD3
+1398	MX6SDL_PAD_RGMII_TD3__GPIO_6_23
+1399	MX6SDL_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4
+1400	MX6SDL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE
+1401	MX6SDL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START
+1402	MX6SDL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL
+1403	MX6SDL_PAD_RGMII_TX_CTL__GPIO_6_26
+1404	MX6SDL_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7
+1405	MX6SDL_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT
+1406	MX6SDL_PAD_RGMII_TXC__USBOH3_H2_DATA
+1407	MX6SDL_PAD_RGMII_TXC__ENET_RGMII_TXC
+1408	MX6SDL_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK
+1409	MX6SDL_PAD_RGMII_TXC__GPIO_6_19
+1410	MX6SDL_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0
+1411	MX6SDL_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT
+1412	MX6SDL_PAD_SD1_CLK__USDHC1_CLK
+1413	MX6SDL_PAD_SD1_CLK__OSC32K_32K_OUT
+1414	MX6SDL_PAD_SD1_CLK__GPT_CLKIN
+1415	MX6SDL_PAD_SD1_CLK__GPIO_1_20
+1416	MX6SDL_PAD_SD1_CLK__PHY_DTB_0
+1417	MX6SDL_PAD_SD1_CMD__USDHC1_CMD
+1418	MX6SDL_PAD_SD1_CMD__PWM4_PWMO
+1419	MX6SDL_PAD_SD1_CMD__GPT_CMPOUT1
+1420	MX6SDL_PAD_SD1_CMD__GPIO_1_18
+1421	MX6SDL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5
+1422	MX6SDL_PAD_SD1_DAT0__USDHC1_DAT0
+1423	MX6SDL_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS
+1424	MX6SDL_PAD_SD1_DAT0__GPT_CAPIN1
+1425	MX6SDL_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8
+1426	MX6SDL_PAD_SD1_DAT0__GPIO_1_16
+1427	MX6SDL_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1
+1428	MX6SDL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7
+1429	MX6SDL_PAD_SD1_DAT1__USDHC1_DAT1
+1430	MX6SDL_PAD_SD1_DAT1__PWM3_PWMO
+1431	MX6SDL_PAD_SD1_DAT1__GPT_CAPIN2
+1432	MX6SDL_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7
+1433	MX6SDL_PAD_SD1_DAT1__GPIO_1_17
+1434	MX6SDL_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0
+1435	MX6SDL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8
+1436	MX6SDL_PAD_SD1_DAT2__USDHC1_DAT2
+1437	MX6SDL_PAD_SD1_DAT2__GPT_CMPOUT2
+1438	MX6SDL_PAD_SD1_DAT2__PWM2_PWMO
+1439	MX6SDL_PAD_SD1_DAT2__WDOG1_WDOG_B
+1440	MX6SDL_PAD_SD1_DAT2__GPIO_1_19
+1441	MX6SDL_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB
+1442	MX6SDL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4
+1443	MX6SDL_PAD_SD1_DAT3__USDHC1_DAT3
+1444	MX6SDL_PAD_SD1_DAT3__GPT_CMPOUT3
+1445	MX6SDL_PAD_SD1_DAT3__PWM1_PWMO
+1446	MX6SDL_PAD_SD1_DAT3__WDOG2_WDOG_B
+1447	MX6SDL_PAD_SD1_DAT3__GPIO_1_21
+1448	MX6SDL_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB
+1449	MX6SDL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6
+1450	MX6SDL_PAD_SD2_CLK__USDHC2_CLK
+1451	MX6SDL_PAD_SD2_CLK__KPP_COL_5
+1452	MX6SDL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS
+1453	MX6SDL_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9
+1454	MX6SDL_PAD_SD2_CLK__GPIO_1_10
+1455	MX6SDL_PAD_SD2_CLK__PHY_DTB_1
+1456	MX6SDL_PAD_SD2_CMD__USDHC2_CMD
+1457	MX6SDL_PAD_SD2_CMD__KPP_ROW_5
+1458	MX6SDL_PAD_SD2_CMD__AUDMUX_AUD4_RXC
+1459	MX6SDL_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10
+1460	MX6SDL_PAD_SD2_CMD__GPIO_1_11
+1461	MX6SDL_PAD_SD2_DAT0__USDHC2_DAT0
+1462	MX6SDL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD
+1463	MX6SDL_PAD_SD2_DAT0__KPP_ROW_7
+1464	MX6SDL_PAD_SD2_DAT0__GPIO_1_15
+1465	MX6SDL_PAD_SD2_DAT0__DCIC2_DCIC_OUT
+1466	MX6SDL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2
+1467	MX6SDL_PAD_SD2_DAT1__USDHC2_DAT1
+1468	MX6SDL_PAD_SD2_DAT1__WEIM_WEIM_CS_2
+1469	MX6SDL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS
+1470	MX6SDL_PAD_SD2_DAT1__KPP_COL_7
+1471	MX6SDL_PAD_SD2_DAT1__GPIO_1_14
+1472	MX6SDL_PAD_SD2_DAT1__CCM_WAIT
+1473	MX6SDL_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0
+1474	MX6SDL_PAD_SD2_DAT2__USDHC2_DAT2
+1475	MX6SDL_PAD_SD2_DAT2__WEIM_WEIM_CS_3
+1476	MX6SDL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD
+1477	MX6SDL_PAD_SD2_DAT2__KPP_ROW_6
+1478	MX6SDL_PAD_SD2_DAT2__GPIO_1_13
+1479	MX6SDL_PAD_SD2_DAT2__CCM_STOP
+1480	MX6SDL_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1
+1481	MX6SDL_PAD_SD2_DAT3__USDHC2_DAT3
+1482	MX6SDL_PAD_SD2_DAT3__KPP_COL_6
+1483	MX6SDL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC
+1484	MX6SDL_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11
+1485	MX6SDL_PAD_SD2_DAT3__GPIO_1_12
+1486	MX6SDL_PAD_SD2_DAT3__SJC_DONE
+1487	MX6SDL_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3
+1488	MX6SDL_PAD_SD3_CLK__USDHC3_CLK
+1489	MX6SDL_PAD_SD3_CLK__UART2_CTS
+1490	MX6SDL_PAD_SD3_CLK__UART2_RTS
+1491	MX6SDL_PAD_SD3_CLK__CAN1_RXCAN
+1492	MX6SDL_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5
+1493	MX6SDL_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5
+1494	MX6SDL_PAD_SD3_CLK__GPIO_7_3
+1495	MX6SDL_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17
+1496	MX6SDL_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14
+1497	MX6SDL_PAD_SD3_CMD__USDHC3_CMD
+1498	MX6SDL_PAD_SD3_CMD__UART2_CTS
+1499	MXSDL_PAD_SD3_CMD__UART2_RTS
+1500	MX6SDL_PAD_SD3_CMD__CAN1_TXCAN
+1501	MX6SDL_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4
+1502	MX6SDL_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4
+1503	MX6SDL_PAD_SD3_CMD__GPIO_7_2
+1504	MX6SDL_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16
+1505	MX6SDL_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13
+1506	MX6SDL_PAD_SD3_DAT0__USDHC3_DAT0
+1507	MX6SDL_PAD_SD3_DAT0__UART1_CTS
+1508	MX6SDL_PAD_SD3_DAT0__UART1_RTS
+1509	MX6SDL_PAD_SD3_DAT0__CAN2_TXCAN
+1510	MX6SDL_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6
+1511	MX6SDL_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6
+1512	MX6SDL_PAD_SD3_DAT0__GPIO_7_4
+1513	MX6SDL_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18
+1514	MX6SDL_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15
+1515	MX6SDL_PAD_SD3_DAT1__USDHC3_DAT1
+1516	MX6SDL_PAD_SD3_DAT1__UART1_CTS
+1517	MX6SDL_PAD_SD3_DAT1__UART1_RTS
+1518	MX6SDL_PAD_SD3_DAT1__CAN2_RXCAN
+1519	MX6SDL_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7
+1520	MX6SDL_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7
+1521	MX6SDL_PAD_SD3_DAT1__GPIO_7_5
+1522	MX6SDL_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19
+1523	MX6SDL_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0
+1524	MX6SDL_PAD_SD3_DAT2__USDHC3_DAT2
+1525	MX6SDL_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28
+1526	MX6SDL_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8
+1527	MX6SDL_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8
+1528	MX6SDL_PAD_SD3_DAT2__GPIO_7_6
+1529	MX6SDL_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20
+1530	MX6SDL_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1
+1531	MX6SDL_PAD_SD3_DAT3__USDHC3_DAT3
+1532	MX6SDL_PAD_SD3_DAT3__UART3_CTS
+1533	MX6SDL_PAD_SD3_DAT3__UART3_RTS
+1534	MX6SDL_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29
+1535	MX6SDL_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9
+1536	MX6SDL_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9
+1537	MX6SDL_PAD_SD3_DAT3__GPIO_7_7
+1538	MX6SDL_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21
+1539	MX6SDL_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2
+1540	MX6SDL_PAD_SD3_DAT4__USDHC3_DAT4
+1541	MX6SDL_PAD_SD3_DAT4__UART2_TXD
+1542	MX6SDL_PAD_SD3_DAT4__UART2_RXD
+1543	MX6SDL_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27
+1544	MX6SDL_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3
+1545	MX6SDL_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3
+1546	MX6SDL_PAD_SD3_DAT4__GPIO_7_1
+1547	MX6SDL_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15
+1548	MX6SDL_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12
+1549	MX6SDL_PAD_SD3_DAT5__USDHC3_DAT5
+1550	MX6SDL_PAD_SD3_DAT5__UART2_TXD
+1551	MX6SDL_PAD_SD3_DAT5__UART2_RXD
+1552	MX6SDL_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26
+1553	MX6SDL_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2
+1554	MX6SDL_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2
+1555	MX6SDL_PAD_SD3_DAT5__GPIO_7_0
+1556	MX6SDL_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14
+1557	MX6SDL_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11
+1558	MX6SDL_PAD_SD3_DAT6__USDHC3_DAT6
+1559	MX6SDL_PAD_SD3_DAT6__UART1_TXD
+1560	MX6SDL_PAD_SD3_DAT6__UART1_RXD
+1561	MX6SDL_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25
+1562	MX6SDL_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1
+1563	MX6SDL_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1
+1564	MX6SDL_PAD_SD3_DAT6__GPIO_6_18
+1565	MX6SDL_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13
+1566	MX6SDL_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10
+1567	MX6SDL_PAD_SD3_DAT7__USDHC3_DAT7
+1568	MX6SDL_PAD_SD3_DAT7__UART1_TXD
+1569	MX6SDL_PAD_SD3_DAT7__UART1_RXD
+1570	MX6SDL_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24
+1571	MX6SDL_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0
+1572	MX6SDL_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0
+1573	MX6SDL_PAD_SD3_DAT7__GPIO_6_17
+1574	MX6SDL_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12
+1575	MX6SDL_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV
+1576	MX6SDL_PAD_SD3_RST__USDHC3_RST
+1577	MX6SDL_PAD_SD3_RST__UART3_CTS
+1578	MX6SDL_PAD_SD3_RST__UART3_RTS
+1579	MX6SDL_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30
+1580	MX6SDL_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10
+1581	MX6SDL_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10
+1582	MX6SDL_PAD_SD3_RST__GPIO_7_8
+1583	MX6SDL_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22
+1584	MX6SDL_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3
+1585	MX6SDL_PAD_SD4_CLK__USDHC4_CLK
+1586	MX6SDL_PAD_SD4_CLK__RAWNAND_WRN
+1587	MX6SDL_PAD_SD4_CLK__UART3_TXD
+1588	MX6SDL_PAD_SD4_CLK__UART3_RXD
+1589	MX6SDL_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6
+1590	MX6SDL_PAD_SD4_CLK__GPIO_7_10
+1591	MX6SDL_PAD_SD4_CMD__USDHC4_CMD
+1592	MX6SDL_PAD_SD4_CMD__RAWNAND_RDN
+1593	MX6SDL_PAD_SD4_CMD__UART3_TXD
+1594	MX6SDL_PAD_SD4_CMD__UART3_RXD
+1595	MX6SDL_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5
+1596	MX6SDL_PAD_SD4_CMD__GPIO_7_9
+1597	MX6SDL_PAD_SD4_DAT0__RAWNAND_D8
+1598	MX6SDL_PAD_SD4_DAT0__USDHC4_DAT0
+1599	MX6SDL_PAD_SD4_DAT0__RAWNAND_DQS
+1600	MX6SDL_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24
+1601	MX6SDL_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24
+1602	MX6SDL_PAD_SD4_DAT0__GPIO_2_8
+1603	MX6SDL_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8
+1604	MX6SDL_PAD_SD4_DAT1__RAWNAND_D9
+1605	MX6SDL_PAD_SD4_DAT1__USDHC4_DAT1
+1606	MX6SDL_PAD_SD4_DAT1__PWM3_PWMO
+1607	MX6SDL_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25
+1608	MX6SDL_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25
+1609	MX6SDL_PAD_SD4_DAT1__GPIO_2_9
+1610	MX6SDL_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9
+1611	MX6SDL_PAD_SD4_DAT2__RAWNAND_D10
+1612	MX6SDL_PAD_SD4_DAT2__USDHC4_DAT2
+1613	MX6SDL_PAD_SD4_DAT2__PWM4_PWMO
+1614	MX6SDL_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26
+1615	MX6SDL_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26
+1616	MX6SDL_PAD_SD4_DAT2__GPIO_2_10
+1617	MX6SDL_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10
+1618	MX6SDL_PAD_SD4_DAT3__RAWNAND_D11
+1619	MX6SDL_PAD_SD4_DAT3__USDHC4_DAT3
+1620	MX6SDL_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27
+1621	MX6SDL_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27
+1622	MX6SDL_PAD_SD4_DAT3__GPIO_2_11
+1623	MX6SDL_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11
+1624	MX6SDL_PAD_SD4_DAT4__RAWNAND_D12
+1625	MX6SDL_PAD_SD4_DAT4__USDHC4_DAT4
+1626	MX6SDL_PAD_SD4_DAT4__UART2_TXD
+1627	MX6SDL_PAD_SD4_DAT4__UART2_RXD
+1628	MX6SDL_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28
+1629	MX6SDL_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28
+1630	MX6SDL_PAD_SD4_DAT4__GPIO_2_12
+1631	MX6SDL_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12
+1632	MX6SDL_PAD_SD4_DAT5__RAWNAND_D13
+1633	MX6SDL_PAD_SD4_DAT5__USDHC4_DAT5
+1634	MX6SDL_PAD_SD4_DAT5__UART2_CTS
+1635	MX6SDL_PAD_SD4_DAT5__UART2_RTS
+1636	MX6SDL_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29
+1637	MX6SDL_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29
+1638	MX6SDL_PAD_SD4_DAT5__GPIO_2_13
+1639	MX6SDL_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13
+1640	MX6SDL_PAD_SD4_DAT6__RAWNAND_D14
+1641	MX6SDL_PAD_SD4_DAT6__USDHC4_DAT6
+1642	MX6SDL_PAD_SD4_DAT6__UART2_CTS
+1643	MX6SDL_PAD_SD4_DAT6__UART2_RTS
+1644	MX6SDL_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30
+1645	MX6SDL_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30
+1646	MX6SDL_PAD_SD4_DAT6__GPIO_2_14
+1647	MX6SDL_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14
+1648	MX6SDL_PAD_SD4_DAT7__RAWNAND_D15
+1649	MX6SDL_PAD_SD4_DAT7__USDHC4_DAT7
+1650	MX6SDL_PAD_SD4_DAT7__UART2_TXD
+1651	MX6SDL_PAD_SD4_DAT7__UART2_RXD
+1652	MX6SDL_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31
+1653	MX6SDL_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31
+1654	MX6SDL_PAD_SD4_DAT7__GPIO_2_15
+1655	MX6SDL_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15