diff options
author | Sheng Nan <b38800@freescale.com> | 2013-03-12 18:35:31 +0800 |
---|---|---|
committer | Sheng Nan <b38800@freescale.com> | 2013-03-14 13:52:28 +0800 |
commit | b94b694b4ee77983c9df5a69555acd7703e91f4c (patch) | |
tree | 6ec5760c340978c970a9701e32af0234f321bb8c /Documentation | |
parent | 7ab543b9c8bcc92a83a507659cbf96be29768a3f (diff) |
ENGR00242180-8: doc: devicetree: mipi-csi2: add doc for mipi csi2
Add ARM devicetree binding document for fsl mipi csi2 on IMX6
Signed-off-by: Sheng Nan <b38800@freescale.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt new file mode 100644 index 000000000000..d74575d484ab --- /dev/null +++ b/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt @@ -0,0 +1,42 @@ +* Freescale MIPI CSI2 Controller for i.MX6DQ/i.MX6SDL + +Required properties for mipi csi2 controller: +- compatible: should be "fsl,imx6q-mipi-csi2" +- reg: <base addr, range> contains mipi csi2 register base address and range +- interrupts: <type num flag> where type is a interrupt type, num is the + interrupt number and flag is a field that level/trigger information for + the interrupt. +- clocks: the clock sources that mipi csi2 depends on. +- clock-names: the name is related to the clock source one by one. +- status: should be set to "disable". + +Required properties for mipi csi2 on specified board: +- ipu_id: ipu id which mipi csi2 connected to. + should be 0 or 1 for i.MX6DQ; should be 0 for i.MX6SDL +- csi_id: csi id which mipi csi2 connected to. + should be 0 or 1 for i.MX6DQ/i.MX6SDL +- v_channel: virtual channel which send to MIPI CSI2 controller + should keep consistent with the input MIPI signal. +- lanes: data lanes of input MIPI signal. The maximum data lanes is 4. + should keep consistent with the input MIPI signal. +- status: should be set to "okay". + +Examples: +for SOC imx6.dtsi: + mipi@021dc000 { /* MIPI-CSI */ + compatible = "fsl,imx6q-mipi-csi2"; + reg = <0x021dc000 0x4000>; + interrupts = <0 100 0x04>, <0 101 0x04>; + clocks = <&clks 138>, <&clks 53>; + clock-names = "dphy_clk", "pixel_clk"; + status = "disabled"; + }; + +for board imx6q-sabresd.dts: + mipi@021dc000 { /* MIPI-CSI */ + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + }; |