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| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2015-01-30 13:41:28 -0600 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-02-11 18:46:41 +0800 |
| commit | 1794fd3c6a2586279a80d1aa580981cdc492ac38 (patch) | |
| tree | facd52d705abeb4f9261375179c90b94138fcb72 /Documentation | |
| parent | eb98c3e690ea59da9b5c278fdfb9b96cade4a80c (diff) | |
MLK-9961-5 cpufreq:imx6x: Change PLL1 clock management.
Add support to leave PLL1 enabled since its required whenever ARM-PODF is
changed. With this patch PLL1 is set to bypassed mode (and enabled) whenever
ARM is sourced from step_clk.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions