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authorMin-wuk Lee <mlee@nvidia.com>2013-07-02 11:18:54 +0900
committerGabby Lee <galee@nvidia.com>2013-10-13 16:30:21 -0700
commit6187da13fbd4880c22d2433a7e61b7728f23fd58 (patch)
tree50a438e2f15a45624ad60f51817d6ea357cbc7d6 /Documentation
parent2df3005f6eb06334902a8303335511735f249328 (diff)
video: tegra: dc: tmds config from device tree
With this change, hdmi tmds config can be set from device tree. Bug 1315829 Bug 1240921 Change-Id: I2551b8012a14a478678fdd821f78beb27c9f779e Signed-off-by: Min-wuk Lee <mlee@nvidia.com> Reviewed-on: http://git-master/r/243864 (cherry picked from commit 1d24765041448f45926b2282b2873a392913fe16) Reviewed-on: http://git-master/r/289698 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Gabby Lee <galee@nvidia.com> Tested-by: Gabby Lee <galee@nvidia.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt23
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
index 0aaba15f1d6c..fd995827e549 100644
--- a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
+++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt
@@ -59,6 +59,29 @@ NVIDIA Tegra114 Display Controller
- nvidia,out-align: Display data alignment. Should be "msb" or "lsb".
- nvidia,out-order: Display data order. Should be "rtob" or "btor".
+ 1.B.i) NVIDIA Display Controller TMDS configurations
+ This must be contained in dc-default-out parent node. This includes tmds configurations.
+
+ Required properties:
+ - name: Should be "nvidia,out-tmds-cfg"
+
+ - Child nodes represent tmds configurations. Several configurations can be prepared.
+
+ 1.B.i.x) NVIDIA Display Controller TMDS configuration
+ This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration.
+
+ Required properties:
+ - name: Can be arbitrary, but each sibling node should have unique name.
+ - pclk: pixel clk required in tmds table for each mode.
+ - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM.
+ - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM.
+ - pe-current: Individual lane pre-emphasis current control (4bits per lane)
+ See HDMI_NV_PDISP_PE_CURRENT_0 in Tegra TRM.
+ - drive-current: TMDS per-lane I/O current control.
+ See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM.
+ - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane.
+ See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM.
+
1.C) NVIDIA Display Controller framebuffer data
This must be contained in dc parent node. This is required framebuffer data.