diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-08-14 14:46:23 +0800 |
|---|---|---|
| committer | Octavian Purdila <octavian.purdila@nxp.com> | 2017-02-23 15:20:38 +0200 |
| commit | f0ec41b5f9494d243e914cca8c7614dd20d34ef0 (patch) | |
| tree | 6677d48e17eaafb426781f67430f6a4aff3cadf6 /Documentation | |
| parent | e8759554c46a24bcb0150db310d3cc844cd0f170 (diff) | |
MLK-11360-01 crypto: caam_snvs: add snvs clock management
caam_snvs driver involves snvs HP registers access that needs to
enable snvs clock source. The patch add the clock management.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index adeca34c5a33..f6e6fba9140b 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -395,6 +395,15 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: <u32> Definition: LP register offset. default it is 0x34. + - clocks + Usage: optional + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. + EXAMPLE sec_mon_rtc_lp@1 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; |