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authorRobin Gong <yibin.gong@nxp.com>2019-04-17 17:05:42 +0800
committerRobin Gong <yibin.gong@nxp.com>2019-07-22 19:15:57 +0800
commit0b6da46b7bdb2284e24757d48466268b9feb5b7c (patch)
tree34af5d51070ca9cf70011bc43440d41cdf8e1828 /Documentation
parent3b2efedfff8a5e0dd4e7b8adbf4d79a704d8a53a (diff)
MLK-22284-1 dmaengine: fsl-edma-v3: add power domains for each channel
Add power domains for each dma channel so that edma channel could know the power state of every dma channel anytime and clear easily unexpected interrupt which triggered before the last partition reset. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/dma/fsl-edma-v3.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
index a8d05427f954..2fb7d1b69604 100644
--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
@@ -30,6 +30,7 @@ Required properties:
0: not dual fifo case, 1: dualfifo case.
See the SoC's reference manual for all the supported request sources.
- dma-channels : Number of channels supported by the controller
+- pdomains: Power domains for edma channel used.
Examples:
edma0: dma-controller@40018000 {
@@ -46,6 +47,8 @@ edma0: dma-controller@40018000 {
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
"edma0-chan14-rx", "edma0-chan15-tx";
+ pdomains = <&pd_dma0_chan12>, <&pd_dma0_chan13>,
+ <&pd_dma0_chan14>, <&pd_dma0_chan15>,
status = "okay";
};