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authorRobby Cai <R63905@freescale.com>2013-08-22 14:35:09 +0800
committerJason Liu <r64343@freescale.com>2013-10-30 09:55:02 +0800
commit2b2df2753f6dfb6345e1eb3124f18d6d4dd9e08e (patch)
treea289c54bb50066c9e3909bb58fb47c6f818d04cd /Documentation
parent48a9dddc8f9fd9a28f28d7f9172a8f0262ebe079 (diff)
ENGR00275031-1 mx6sl fb: support lcdif framebuffer on 3.10
re-use the upstreaming mxsfb.c code. - add the lcdif axi clock for register and dram access - set the lcdif pix's parent as pll5_video to get most accurate pix clock - add binding doc for lcdif dts Signed-off-by: Robby Cai <R63905@freescale.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/fb/mxsfb.txt7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fb/mxsfb.txt b/Documentation/devicetree/bindings/fb/mxsfb.txt
index 96ec5179c8a0..db41376d503e 100644
--- a/Documentation/devicetree/bindings/fb/mxsfb.txt
+++ b/Documentation/devicetree/bindings/fb/mxsfb.txt
@@ -3,6 +3,9 @@
Required properties:
- compatible: Should be "fsl,<chip>-lcdif". Supported chips include
imx23 and imx28.
+- pinctrl-names: Should be "default"
+- pinctrl-0: pinctrl setting for lcd
+- lcd-supply: lcd power supply, usually via GPIO
- reg: Address and length of the register set for lcdif
- interrupts: Should contain lcdif interrupts
- display : phandle to display node (see below for details)
@@ -22,6 +25,10 @@ lcdif@80030000 {
compatible = "fsl,imx28-lcdif";
reg = <0x80030000 2000>;
interrupts = <38 86>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_evk>;
+ lcd-supply = <&reg_lcd_3v3>;
display: display {
bits-per-pixel = <32>;