diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-07-17 15:08:07 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2019-07-18 18:04:40 +0800 |
| commit | 3b2efedfff8a5e0dd4e7b8adbf4d79a704d8a53a (patch) | |
| tree | aad8576b9f85479d60d8176f6f629b0e50f83189 /Documentation | |
| parent | ca92e291116ccb2f052976d4af17a4da713d8c7f (diff) | |
MLK-22252 phy: mixel-lvds-combo: Configure CO divider to meet fvco range requirement
As the below diagram shows, to achieve a particular serial clock rate,
we should choose an appropriate CO divider value(1/2/4/8) so that PLL
VCO frequency(fvco) is in specified range(640MHz ~ 1500MHz).
--------- 640MHz ~ 1500MHz ------------ --------------
| PLL VCO | ----------------> | CO divider | -> | serial clock |
--------- ------------ --------------
1/2/4/8 div 7 * phy_clk_rate
This patch configures CO divider to be appropriate value to meet the fvco
range requirement. This may address display flicker issue seen on some
SoC samples.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 720ed81158607cefecec7a3f7c53680aff251139)
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions