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authorDong Aisheng <aisheng.dong@nxp.com>2017-05-10 15:04:14 +0800
committerAnson Huang <Anson.Huang@nxp.com>2017-06-09 22:20:16 +0800
commit941af2f0a0ef9ebfd8a2245cbe7017b6ac5a9969 (patch)
tree1ec0327a1ce351e8764b1f235f5588a93c637d6d /Documentation
parent3af431549119943d66b1028207918105024e6a64 (diff)
MLK-14866-1 dt-bindings: pinctrl: add imx7ulp binding doc
Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and config register as follows: <mux_conf_reg input_reg mux_mode input_val> Also fix the copyright. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt33
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diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
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+* Freescale i.MX7ULP IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx7ulp-iomuxc-0" or "fsl,imx7ulp-iomuxc-1"
+- fsl,pins: two integers array, represents a group of pins mux and config
+ setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+ pin working on a specific function, CONFIG is the pad setting value like
+ pull-up for this pin. Please refer to imx7ulp datasheet for the valid pad
+ config settings.
+
+NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux and
+config register as follows:
+<mux_conf_reg input_reg mux_mode input_val>
+
+CONFIG bits definition:
+PAD_CTL_OBE (1 << 17)
+PAD_CTL_IBE (1 << 16)
+PAD_CTL_LK (1 << 15)
+PAD_CTL_DSE_HIGH (1 << 6)
+PAD_CTL_DSE_STD (0 << 6)
+PAD_CTL_ODE_OPEN_DRAIN (1 << 5)
+PAD_CTL_ODE_PUSH_PULL (0 << 5)
+PAD_CTL_SRE_SLOW (1 << 2)
+PAD_CTL_SRE_STD (0 << 2)
+PAD_CTL_PE_PULL (1 << 1)
+PAD_CTL_PS_UP (1 << 0)
+PAD_CTL_PS_DOWN (0 << 0)
+
+Refer to imx7ulp-pinfunc.h in device tree source folder for all available
+imx7ulp PIN_FUNC_ID.