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authorStefan Agner <stefan@agner.ch>2016-02-11 18:36:54 -0800
committerStefan Agner <stefan@agner.ch>2016-02-11 18:36:54 -0800
commit5d1261e1f2ad61553d80efb3ee3c47040c8ded2e (patch)
tree0dd9cb3aa7283fd1bc11a538de192abd73a99556 /Documentation
parent9640e3b7fbab5246b5ef4f851eb49cea476729bf (diff)
parentc4d0c9e623d7a950f35d88f9ec23bb6b894fe374 (diff)
Merge branch 'vf610-suspend-4.4-lpstop2' into toradex_vf_4.4-next
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,vf610-ddrmc.txt23
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+Freescale Vybrid LPDDR2/DDR3 SDRAM Memory Controller
+
+The memory controller supports high performance applications for 16-bit or
+8-bit DDR2, or LPDDR SDRAM memories.
+
+Required properties:
+- compatible: "fsl,vf610-ddrmc"
+- reg: the register range of the DDRMC registers
+- clocks: DDRMC main clock to clock memory and access registers.
+- clock-names: Must contain "ddrc", matching entry in the clocks property.
+- fsl,has-cke-reset-pulls:
+ States whether pull-down/up are populated on DDR CKE/RESET
+ signals to allow using DDR self-refresh modes (see Vybrid
+ Hardware Development Guide for details).
+
+Example:
+ ddrmc: ddrmc@400ae000 {
+ compatible = "fsl,vf610-ddrmc";
+ reg = <0x400ae000 0x1000>;
+ clocks = <&clks VF610_CLK_DDRMC>;
+ clock-names = "ddrc";
+ fsl,has-cke-reset-pulls;
+ }