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| author | Peter Chen <peter.chen@freescale.com> | 2015-02-04 16:20:33 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:21:31 -0500 |
| commit | b34a614da1918d7426b488d3ceb17fcae5c0756a (patch) | |
| tree | dc99c9a692fda4c85183171b06e6228a9f023403 /Documentation | |
| parent | 5cbb2ee982ea273cc2383f1e25f2839f24b03004 (diff) | |
MLK-10202-2 doc: usb: mxs-phy: add tx-d-cal property
Add tx-d-cal property
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/usb/mxs-phy.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt index 379b84a567cc..a3b6055bec15 100644 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt @@ -12,10 +12,16 @@ Required properties: - interrupts: Should contain phy interrupt - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series +Optional properties: +- tx-d-cal: Try to adjust this value to improve signal quality, and pass + USB Certification, the value is from 0x0 to 0xf, and the register offset + is 0x10 (USBPHY_TX). + Example: usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; fsl,anatop = <&anatop>; + tx-d-cal = <0x5>; }; |