MLK-17537-8: drm/mxsfb: Add support for mode_valid

Implement mode_valid and check functions from
drm_simple_display_pipe_funcs such that we can filter-out modes that
cannot be driven by this controller.
Add 3 new clocks:
- video_pll: this is the PLL that provides the pixel clock; it's rate
  needs to be set such that the pixel clock can be achieved
- osc_25: this is an oscillater that can be used as source clock for the
  video_pll; default freq is 25MHz
- osc_27: same as above, but with freq of 27MHz

Depending on the display mode used, the video_pll needs to have it's
clock source a 25MHz or 27MHz oscillator. Also, the video_pll rate needs
to be set to a rate that can be evenly divided to obtain the required
pixel clock. All these settings (clock source and video_pll rate) are
saved in mode_valid, then applied before mode needs to be set in the
check function.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt
index 7040fb0dfa2b..234481c5d52d 100644
--- a/Documentation/devicetree/bindings/display/mxsfb.txt
+++ b/Documentation/devicetree/bindings/display/mxsfb.txt
@@ -13,6 +13,8 @@ Required properties:
 - clock-names:	A list of clock names. For MXSFB it should contain:
     - "pix" for the LCDIF block clock
     - (MX6SX-only) "axi", "disp_axi" for the bus interface clock
+    - (MX8-only) "video_pll, "osc_25", "osc_27" for the VIDEO_PLL,
+      OSC_25M and OSC_27M clocks
 
 Required sub-nodes:
   - port: The connection to an encoder chip.