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authorChew, Kean ho <kean.ho.chew@intel.com>2014-03-01 00:03:56 +0800
committerJiri Slaby <jslaby@suse.cz>2014-05-05 11:26:00 +0200
commit008c29f91e856d2e46104c082baaa518832bd2a3 (patch)
tree365a1e2f3dde3bb87cc44120e4a068d747a3a41b /Documentation
parentaeaf64c5a760c88e7af7b316536980d41bf312cf (diff)
i2c: i801: enable Intel BayTrail SMBUS
commit 1b31e9b76ef8c62291e698dfdb973499986a7f68 upstream. Add Device ID of Intel BayTrail SMBus Controller. Signed-off-by: Chew, Kean ho <kean.ho.chew@intel.com> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/i2c/busses/i2c-i8011
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index 7b0dcdb57173..babe2ef16139 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -26,6 +26,7 @@ Supported adapters:
* Intel Wellsburg (PCH)
* Intel Coleto Creek (PCH)
* Intel Wildcat Point-LP (PCH)
+ * Intel BayTrail (SOC)
Datasheets: Publicly available at the Intel website
On Intel Patsburg and later chipsets, both the normal host SMBus controller