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| author | Otavio Salvador <otavio@ossystems.com.br> | 2019-03-28 10:47:24 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-28 10:47:24 -0300 |
| commit | 0a8ab17689e628c84a666195bfc6ab85d11cf057 (patch) | |
| tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /arch/arc/include/asm/cache.h | |
| parent | 1e71d8c630cbc0d1f5d762fd019690b5cdb880ae (diff) | |
| parent | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (diff) | |
Merge pull request #46 from toradex/4.9-2.3.x-imx
4.9 2.3.x imx
Diffstat (limited to 'arch/arc/include/asm/cache.h')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 4fd6272e6c01..c5816a224571 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -49,6 +49,17 @@ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES +/* + * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses + * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit + * alignment for any atomic64_t embedded in buffer. + * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed + * value of 4 (and not 8) in ARC ABI. + */ +#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC) +#define ARCH_SLAB_MINALIGN 8 +#endif + extern void arc_cache_init(void); extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len); extern void read_decode_cache_bcr(void); |