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authorVineet Gupta <vgupta@synopsys.com>2013-06-17 14:33:15 +0530
committerVineet Gupta <vgupta@synopsys.com>2013-06-27 14:37:57 +0530
commitdc81df244028e0d07c8723e3f7ebd1a35e848293 (patch)
tree40aafc02150025631b15dc514469ff74318e71e6 /arch/arc
parentc3e757a77cab461d11cd3e365d700e8c8fb3fae0 (diff)
ARC: [tlb-miss] Fix bug with CONFIG_ARC_DBG_TLB_MISS_COUNT
LOAD_FAULT_PTE macro is expected to set r2 with faulting vaddr. However in case of CONFIG_ARC_DBG_TLB_MISS_COUNT, it was getting clobbered with statistics collection code. Fix latter by using a different register. Note that only I-TLB Miss handler was potentially affected. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/mm/tlbex.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index fcdc19ff6da7..5c5bb23001b0 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -147,9 +147,9 @@ ex_saved_reg1:
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
and.f 0, r0, _PAGE_PRESENT
bz 1f
- ld r2, [num_pte_not_present]
- add r2, r2, 1
- st r2, [num_pte_not_present]
+ ld r3, [num_pte_not_present]
+ add r3, r3, 1
+ st r3, [num_pte_not_present]
1:
#endif
@@ -271,7 +271,7 @@ ARC_ENTRY EV_TLBMissI
#endif
;----------------------------------------------------------------
- ; Get the PTE corresponding to V-addr accessed
+ ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
LOAD_FAULT_PTE
;----------------------------------------------------------------
@@ -311,7 +311,7 @@ ARC_ENTRY EV_TLBMissD
;----------------------------------------------------------------
; Get the PTE corresponding to V-addr accessed
- ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE
+ ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
LOAD_FAULT_PTE
;----------------------------------------------------------------