diff options
| author | Krishna Reddy <vdumpa@nvidia.com> | 2012-04-11 11:20:20 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-05-04 10:41:33 -0700 |
| commit | ca0eb6c1daef8dc485870596fb6c21354fcbe1e8 (patch) | |
| tree | 84c57b671b1dd201816c98a1bcf131b5abca7a02 /arch/arm/Kconfig | |
| parent | 537d97965a480c9eed3d0db1d16e6d17cfb640ec (diff) | |
ARM: errata: 716044: an uncacheable load multiple can cause a deadlock.
Under some rare circumstances, an uncacheable load multiple
instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause
a processor deadlock.
Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/95914
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3c3b868948aa..fcbd87b17507 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1155,6 +1155,14 @@ config ARM_ERRATA_460075 ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode. +config ARM_ERRATA_716044 + bool "ARM errata: an uncacheable load multiple instruction can cause a deadlock" + depends on CPU_V7 + help + Under some rare circumstances, an uncacheable load multiple + instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause + a processor deadlock. + config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" depends on CPU_V7 && SMP |