diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-14 15:33:34 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-14 15:33:34 +0530 |
| commit | 638bc555a05c39ced59744c79c0461536782808d (patch) | |
| tree | 42bf9c8cdfd44898be31bc31cf2e4743a2484cf4 /arch/arm/Kconfig | |
| parent | f05a661e2247076a0c0e5a09ee8c4397b0de855e (diff) | |
| parent | caf4b0430be8296bf644199bf3ed3056c02420c7 (diff) | |
Merge branch 'linux-3.1.5' into android-tegra-nv-3.1
Conflicts:
arch/arm/Kconfig
Change-Id: If8aaaf3efcbbf6c9017b38efb6d76ef933f147fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 18d45b5ce4bd..0fc94de7c426 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1321,6 +1321,18 @@ config ARM_ERRATA_752520 and MMU are enabled, with the TLB descriptors marked as L1 cacheable, so that Page Table Walks are performed as cache linefills. +config PL310_ERRATA_769419 + bool "PL310 errata: no automatic Store Buffer drain" + depends on CACHE_L2X0 + help + On revisions of the PL310 prior to r3p2, the Store Buffer does + not automatically drain. This can cause normal, non-cacheable + writes to be retained when the memory system is idle, leading + to suboptimal I/O performance for drivers using coherent DMA. + This option adds a write barrier to the cpu_idle loop so that, + on systems with an outer cache, the store buffer is drained + explicitly. + endmenu source "arch/arm/common/Kconfig" |