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authorWill Deacon <will.deacon@arm.com>2011-02-28 18:15:16 +0100
committerJason Liu <r64343@freescale.com>2011-09-23 10:47:39 +0800
commit27bde847de29606da81a543ba6a6f4229460b002 (patch)
tree727493b424126a7790f296613c5b872fd9ccb8bd /arch/arm/Kconfig
parent1a0acc12546bf9516a6207d3021e6117f6f7d95d (diff)
ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
On the r2p* and r3p* versions of the Cortex-A9, a speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 597b7bd28228..efdaf57e5668 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1242,6 +1242,18 @@ config PL310_ERRATA_727915
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean &
Invalidate by Way operation.
+
+config ARM_ERRATA_754322
+ bool "ARM errata: possible faulty MMU translations following an ASID switch"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 754322 Cortex-A9 (r2p*,
+ r3p*) erratum. A speculative memory access may cause a page table walk
+ which starts prior to an ASID switch but completes afterwards. This
+ can populate the micro-TLB with a stale entry which may be hit with
+ the new ASID. This workaround places two dsb instructions in the mm
+ switching code so that no page table walks can cross the ASID switch.
+
endmenu
source "arch/arm/common/Kconfig"