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authorLokesh Vutla <lokeshvutla@ti.com>2016-02-24 15:41:04 +0530
committerTony Lindgren <tony@atomide.com>2016-02-29 15:02:15 -0800
commitdae320ec31736865d22bfac78717726b6545ff41 (patch)
tree727c00770423f7513af069014f376aa65eb89c0a /arch/arm/boot/dts/am57xx-beagle-x15.dts
parent4d91e285483bf6a93d84a483ec0921b86bbc3d24 (diff)
ARM: dts: DRA7: change address-cells and size-cells
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to represent this in memory dt node, the address-cells and size cells should be 2. So, changing the address-cells and size-cells to 2 and updating the memory nodes accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am57xx-beagle-x15.dts')
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 50312f80b972..9b664c58e395 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -24,7 +24,7 @@
memory {
device_type = "memory";
- reg = <0x80000000 0x80000000>;
+ reg = <0x0 0x80000000 0x0 0x80000000>;
};
vdd_3v3: fixedregulator-vdd_3v3 {