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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2015-06-11 13:51:12 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-07-09 14:25:28 +0200 |
| commit | c8f5a878e55459b78bac273f6492bbc91475beb5 (patch) | |
| tree | 922d9159d6dcf7fdee7dfe37651f7a30ced01688 /arch/arm/boot/dts/armada-375.dtsi | |
| parent | 449e1d649c52a80db73dd313dce92d6e191b801b (diff) | |
ARM: mvebu: use DT properties to fine-tune the L2 configuration
In order to optimize the L2 cache performance, this commit adjusts the
configuration of the L2 on the Cortex-A9 based Marvell EBU processors
(Armada 375, 38x and 39x), using the appropriate DT properties.
We enable double linefill, incr double linefill, data prefetch and
disable double linefill on wrap. This matches the configuration that
was fine tuned in the Marvell BSP.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-375.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-375.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 67a0ab0f71e0..e9a381741ce1 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -176,6 +176,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <1>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <1>; + prefetch-data = <1>; }; scu@c000 { |