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authorGregory CLEMENT <gregory.clement@free-electrons.com>2016-11-05 19:03:50 +0100
committerGregory CLEMENT <gregory.clement@free-electrons.com>2016-11-19 09:16:35 +0100
commit007d05d898050ffc70fd2737896528c5069f7269 (patch)
tree18ebf273fc48790e82a3e1ab14cb02a9bfaffe6c /arch/arm/boot/dts/armada-xp-gp.dts
parent1fc2129553c5a387be786c4b302e3a253a7d01a8 (diff)
ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-gp.dts')
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts42
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 09c9cabdf67a..fca37e92b96a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -127,27 +127,6 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie@10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial@12000 {
status = "okay";
@@ -233,6 +212,27 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie@1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie@9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie@10,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;