diff options
| author | Jisheng Zhang <Jisheng.Zhang@synaptics.com> | 2018-04-27 17:25:15 +0800 |
|---|---|---|
| committer | Jisheng Zhang <Jisheng.Zhang@synaptics.com> | 2018-05-24 15:15:49 +0800 |
| commit | 01d433d594bb6869c12ad109aff4a43eb37d8b33 (patch) | |
| tree | fcc2c139aab1786167d484472bb4390bd306d972 /arch/arm/boot/dts/berlin2q.dtsi | |
| parent | c8e96e070378a14817ab286a9c69a2d64546f788 (diff) | |
ARM: dts: berlin2q: add interrupt-affinity to pmu node
Add interrupt-affinity property to fix below warning:
[ 0.429642] CPU PMU: Failed to parse /soc/pmu/interrupt-affinity[0]
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/berlin2q.dtsi | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index bf3a6c9a1d34..e23c49ae3ec2 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -53,7 +53,7 @@ #size-cells = <0>; enable-method = "marvell,berlin-smp"; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; @@ -71,21 +71,21 @@ >; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; next-level-cache = <&l2>; @@ -113,6 +113,10 @@ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; sdhci0: sdhci@ab0000 { |