diff options
| author | Jisheng Zhang <Jisheng.Zhang@synaptics.com> | 2018-05-15 18:16:23 +0800 |
|---|---|---|
| committer | Jisheng Zhang <Jisheng.Zhang@synaptics.com> | 2018-05-24 15:25:44 +0800 |
| commit | 15cf848d3c208159410eff2055494163c2542bbb (patch) | |
| tree | 4480f274dbcc4e1260e8b1cfe9ed23a564efc3d8 /arch/arm/boot/dts/berlin2q.dtsi | |
| parent | b64ffdecfa84892b15740fbf1c5f180f55646259 (diff) | |
ARM: dts: berlin2q: move PMU node from soc to root
Fix "make dtbs W=1" warns about missing reg or ranges property.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/berlin2q.dtsi | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 82e176011d36..516a7ce25791 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -62,6 +62,19 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; @@ -76,18 +89,6 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; |