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authorAntoine Ténart <antoine.tenart@free-electrons.com>2014-07-30 20:14:00 +0200
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-10-29 19:44:28 +0100
commit70a2b717d0a32d4702ae45880fc1370d9ce93ec0 (patch)
treec9d304f321937d0859fd961db31050bbcd1d21b6 /arch/arm/boot/dts/berlin2q.dtsi
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
ARM: dts: berlin: add the AHCI node for the BG2Q
The BG2Q has an AHCI SATA controller. Add the corresponding nodes (AHCI, PHY) into its device tree. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2q.dtsi')
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..c96a0135f0f8 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -364,6 +364,45 @@
};
};
+ ahci: sata@e90000 {
+ compatible = "marvell,berlin2q-ahci", "generic-ahci";
+ reg = <0xe90000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ status = "disabled";
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ status = "disabled";
+ };
+ };
+
+ sata_phy: phy@e900a0 {
+ compatible = "marvell,berlin2q-sata-phy";
+ reg = <0xe900a0 0x200>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ sata-phy@0 {
+ reg = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ };
+ };
+
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;