diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-12-09 08:22:11 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-12-28 19:26:57 +0200 |
| commit | f3a3a3bf7103faa0c6bd16a26caef0118fc58163 (patch) | |
| tree | 17815333de5f73cc1fb5b30109e48e2f8b09d20a /arch/arm/boot/dts/exynos4412-odroid-common.dtsi | |
| parent | 087ce39cdf4b0a95344ae18676017aacfe51b954 (diff) | |
ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards
Move assigned clocks properties from sound node to audio subsystem clock
controller node. This way clocks topology and rates are set just after
probing audio clocks controller. Leaving those properties under
sound node doesn't guarantee to configure them before they are being used
(for example i2s hardware module can be probed in parallel and it also
require proper audio clocks configuration).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4412-odroid-common.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 7815efd5a52f..b6b0f509f07c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -43,16 +43,6 @@ sound: sound { compatible = "simple-audio-card"; - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <192000000>, - <19200000>; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&link0_codec>; @@ -157,6 +147,16 @@ status = "okay"; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, <0>, <192000000>, <19200000>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; |