diff options
| author | Andrzej Hajda <a.hajda@samsung.com> | 2015-03-18 02:14:07 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-03-18 02:14:07 +0900 |
| commit | fa87bd4360ab4244467571f4235ccb2b362fea24 (patch) | |
| tree | 9abb6a33364af397735d2663c0e3e6527fabcb80 /arch/arm/boot/dts/exynos5420.dtsi | |
| parent | ffb8b1ee9a704229f0b6753970ae09dc4d6863d9 (diff) | |
ARM: dts: add async-bridge clocks to gsc power domain for exynos5420
Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index ac0fc09cdb40..d4d643eac6b7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -251,6 +251,8 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "asb0", "asb1"; }; isp_pd: power-domain@10044020 { |