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authorJavier Martinez Canillas <javier.martinez@collabora.co.uk>2014-09-24 00:16:45 +0900
committerKukjin Kim <kgene.kim@samsung.com>2014-10-21 00:12:40 +0900
commitfa781ddab92909ae06c83cf14dea09eda81d7ba4 (patch)
tree8ce6cebb6fbbb068d861d5156725ddb88a01f4e4 /arch/arm/boot/dts/exynos5800-peach-pi.dts
parent5e794de514f56de1e78e979ca09c56a91aa2e9f1 (diff)
ARM: dts: Add rtc_src clk for s3c-rtc on exynos Peach boards
commit 546b117fdf17 ("rtc: s3c: add support for RTC of Exynos3250 SoC") added an "rtc_src" DT property for the Samsung's S3C Real Time Clock controller that specifies the 32.768 kHz clock that uses the RTC as its source clock. In the case of the Peach Pit and Pi machines, the Maxim 77802 32kHz AP clock is used as the source clock. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5800-peach-pi.dts')
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7bb1c8dd42dd..fdbcec693b6d 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77802.h>
#include "exynos5800.dtsi"
/ {
@@ -150,7 +151,7 @@
status = "okay";
clock-frequency = <400000>;
- max77802-pmic@9 {
+ max77802: max77802-pmic@9 {
compatible = "maxim,max77802";
interrupt-parent = <&gpx3>;
interrupts = <1 IRQ_TYPE_NONE>;
@@ -715,6 +716,8 @@
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+ clock-names = "rtc", "rtc_src";
};
&spi_2 {