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authorLinus Walleij <linus.walleij@linaro.org>2018-10-11 20:06:23 +0200
committerLinus Walleij <linus.walleij@linaro.org>2018-12-08 23:19:23 +0100
commit137cd7100ec6fa36d610e106df00acb4d8af99df (patch)
tree412aa4b55c8ad5152bae9f94b1a28dc37104fe3a /arch/arm/boot/dts/gemini-sq201.dts
parent738a05e673435afb986b53da43befd83ad87ec3b (diff)
ARM: dts: Enable Gemini flash access
Some Gemini platforms have a parallel NOR flash which conflicts with use cases reusing some of the flash lines (such as CE1) for GPIO. Fix this on the D-Link DIR-685 and Itian SQ201 by creating "enabled" and "disabled" states for the flash pin control handle, and rely on the flash handling code to switch this in and out when accessed so these lines can be used for GPIO when flash is not accessed, and enable flash access. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/gemini-sq201.dts')
-rw-r--r--arch/arm/boot/dts/gemini-sq201.dts31
1 files changed, 17 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts
index 3787cf3763c4..af4be6ecb02c 100644
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -41,14 +41,12 @@
compatible = "gpio-leds";
led-green-info {
label = "sq201:green:info";
- /* Conflict with parallel flash */
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-green-usb {
label = "sq201:green:usb";
- /* Conflict with parallel and NAND flash */
gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "usb-host";
@@ -126,15 +124,10 @@
soc {
flash@30000000 {
- /*
- * Flash access can be enabled, with the side effect
- * of disabling access to GPIO LED on GPIO0[20] which
- * reuse one of the parallel flash chip select lines.
- * Also the default firmware on the machine has the
- * problem that since it uses the flash, the two LEDS
- * on the right become numb.
- */
- /* status = "okay"; */
+ status = "okay";
+ pinctrl-names = "enabled", "disabled";
+ pinctrl-0 = <&pflash_default_pins>;
+ pinctrl-1 = <&pflash_disabled_pins>;
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
@@ -184,9 +177,7 @@
mux {
function = "gpio0";
groups = "gpio0fgrp",
- "gpio0ggrp",
- "gpio0hgrp",
- "gpio0kgrp";
+ "gpio0hgrp";
};
};
/*
@@ -199,6 +190,18 @@
groups = "gpio1dgrp";
};
};
+ /*
+ * These GPIO groups will be mapped in over some
+ * of the flash pins when the flash is not in
+ * active use.
+ */
+ pflash_disabled_pins: pinctrl-pflash-disabled {
+ mux {
+ function = "gpio0";
+ groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
+ "gpio0kgrp";
+ };
+ };
pinctrl-gmii {
mux {
function = "gmii";