diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2013-06-08 18:39:37 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 16:04:30 +0800 |
| commit | 0e7b01aad29f6f64c9ad5685ea3ec6dbe38735fa (patch) | |
| tree | 6bc268a9b1955bb2e8f3de9a521aea7eb3fd2f8a /arch/arm/boot/dts/imx27.dtsi | |
| parent | b858c34fd04b2ebb0e7d6c530eb2ce8f32aac48f (diff) | |
ARM: dts: i.MX27: Add SDHC devicetree nodes
This patch adds the missing SDHC devicetree nodes for i.MX27 SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutonix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx27.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx27.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 9d65734b146e..587f10c83be6 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -178,6 +178,28 @@ status = "disabled"; }; + sdhci1: sdhci@10013000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10013000 0x1000>; + interrupts = <11>; + clocks = <&clks 30>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 7>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@10014000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x10014000 0x1000>; + interrupts = <10>; + clocks = <&clks 29>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 6>; + dma-names = "rx-tx"; + status = "disabled"; + }; + gpio1: gpio@10015000 { compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; reg = <0x10015000 0x100>; @@ -293,6 +315,17 @@ status = "disabled"; }; + sdhci3: sdhci@1001e000 { + compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; + reg = <0x1001e000 0x1000>; + interrupts = <9>; + clocks = <&clks 28>, <&clks 60>; + clock-names = "ipg", "per"; + dmas = <&dma 36>; + dma-names = "rx-tx"; + status = "disabled"; + }; + gpt6: timer@1001f000 { compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; reg = <0x1001f000 0x1000>; |