diff options
| author | Akshay Bhat <akshay.bhat@timesys.com> | 2016-04-18 17:19:44 -0400 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-04-26 11:05:30 +0800 |
| commit | b492b8744da9b205b9b303b111a138b16d56e712 (patch) | |
| tree | a5f5917a3a7303f3d56f5fe20f4cfd023d8e37cb /arch/arm/boot/dts/imx6q-b850v3.dts | |
| parent | 7532c98f3ac212ca1f19be7e628356247b616c74 (diff) | |
ARM: dts: imx6q-b850v3: Update display clock source
The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-b850v3.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6q-b850v3.dts | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index dc4b06f27d38..167f7446722a 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -53,11 +53,18 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&ldb { fsl,dual-channel; status = "okay"; |