diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2018-04-23 23:55:49 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:17 +0800 |
| commit | 95e6e2c6500c1c29e3c4d9b08bd9c909f86887e6 (patch) | |
| tree | 121ac7f972299d3f896850f973be887a787f2c38 /arch/arm/boot/dts/imx6q.dtsi | |
| parent | 45f8c8d7741e5e067a5e40fbc6995cf27abcc141 (diff) | |
MGS-3705-1 gpu: dts: enable gpu devices for imx6
set GPU baseAddress with 256M on IMX6Q and iMX6QP,
add reserved cma in DTB to support different size,
the default cma size is 320M on all imx6 boards.
integrated patches from imx_4.9.y:
1.MGS-955 GPU:Integrate GPU module
commit: 73183c14a20d4f1d02317f80db3d90b3be1546fc
2.MGS-1211 gpu: add GPU for 6sl,6sx,6dl
commit: 80a8994c47cbb97fb31ef0efab92ddb29002448e
3.MGS-1087 gpu: Move the GPU reserved memory to DTS file
commit: ea0111da6892b52c790da607a3d91140d1ebf936
4.MGS-2540 [#ccc] Need set baseAddress with RAM start address on IMX6Q
commit: de838d99d9264884cbaaa601ab323a70b62634d9
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 63119e8eafb7..6e7d5afbe87b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -84,6 +84,20 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + soc { busfreq: busfreq { compatible = "fsl,imx_busfreq"; @@ -96,6 +110,29 @@ fsl,max_ddr_freq = <528000000>; }; + gpu: gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; + ocram: sram@00905000 { compatible = "mmio-sram"; reg = <0x00905000 0x3B000>; |