diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2015-06-29 20:08:56 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2015-07-15 10:20:33 +0800 |
| commit | 3ee12d8079a5996f3c85e0890d76c0fcb1749bab (patch) | |
| tree | 712cb7d90d68c31ee0b818e2c55c5b885f1b136d /arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | |
| parent | 366c595f1381b89c52153f753a6499c349410a02 (diff) | |
ARM: dts: ventana: add UHS-I support for Ventana boards
UHS-I support is available on Ventana boards with micro-SD sockets depending
on the board revision. To support this pinctl states for 100Mhz and 200MHz
must be added as well as pinmux of the VSELECT signal. In order to support
UHS-I the I/O rail of the 4-bit data bus must be switchable between 1.8V
and 3.3V.
By adding the no-1-8-v property, which disables UHS-I support, we allow the
bootloader to be in charge of selecting which boards have this capability
by removing that property if the board model/revision implement the support.
Additionally we will remove NANDF_CS1 here from the nand pinmux group as the
second chip-select is not used on any ventana boards and this is the pad
that is used for SD3_VELECT.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-gw52xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 35 |
1 files changed, 32 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index b5756c21ea1d..b8e35513aed2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -316,10 +316,13 @@ }; &usdhc3 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_3p3v>; + no-1-8-v; /* firmware will remove if board revision supports */ status = "okay"; }; @@ -380,7 +383,6 @@ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 @@ -469,7 +471,34 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; }; |