diff options
| author | Shawn Guo <shawn.guo@freescale.com> | 2013-07-14 22:17:16 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 08:57:42 -0500 |
| commit | 4642e486488ffb2e6d0ef2e88be4673a78de80c3 (patch) | |
| tree | 7c063c5c9198b367e047597e619cac728e977e68 /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
| parent | a33c2bc36f04ebd079f28da4ec9efc0bea8ff798 (diff) | |
ENGR00269945: ARM: dts: add max7310 support for imx6qdl-sabreauto
On imx6qdl-sabreauto board, there are three IO expanders implemented by
max7310, which are all controlled by I2C3. And GPIO5_4 is steering the
I2C3_SDA availability, while GPIO1_15 is used to reset max7310.
[shawn.guo: cherry-pick commit b938a6cb0d4c from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Conflicts:
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 5fb41afad287..b6c6fb2f1308 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -22,6 +22,13 @@ spdif-controller = <&spdif>; spdif-in; }; + + max7310_reset: max7310-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; }; &ecspi1 { @@ -53,6 +60,35 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7310_a: gpio@30 { + compatible = "maxim,max7310"; + reg = <0x30>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7310_reset>; + }; + + max7310_b: gpio@32 { + compatible = "maxim,max7310"; + reg = <0x32>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_c: gpio@34 { + compatible = "maxim,max7310"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -63,6 +99,8 @@ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000 >; }; @@ -122,6 +160,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 |