diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-07-03 15:42:09 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:42 +0800 |
| commit | bf81727f2109e59a732a074de6e7595bde567d01 (patch) | |
| tree | d1347bcb3b07d5891898422758d6c425c15ae0b0 /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
| parent | fe5efc9cf62c891bd9b04fefa11eeab60292daa9 (diff) | |
arm64: dts: enable MLB for imx6dl-sabresdauto
Because the pin conflict between fec and mlb, add a
imx6dl-sabreauto-enetirq.dts to avoid the conflict.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index cf628465cd0a..57b84e885dc6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -295,8 +295,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; status = "okay"; }; @@ -511,6 +509,11 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -636,6 +639,14 @@ >; }; + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 @@ -799,6 +810,12 @@ }; }; +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; |