diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-10-11 14:02:31 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:08:28 +0800 |
| commit | a92d83813f60e2dd6e607bc0dd9cedd4ebfafd24 (patch) | |
| tree | 491f65c62ce8209ce3fdb232f72fedf89866f8dd /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
| parent | 10cc7dba5b8848ffc2945ece2e3fb903b7f143ee (diff) | |
ARM: imx6qdl-sabreauto.dtsi: Change LDB_DI0/1_SEL clk's parent to PLL2_PFD0_352M
This patch changes LDB_DI0/1_SEL clock's parent from PLL3_USB_OTG to
PLL2_PFD0_352M so that it aligns with imx_4.19.y kernel. Also, with
this patch applied, the clock tree may provide ~64.6MHz pixel clock
rate to the Hannstar XGA LVDS panel, which is closer to the desired
65MHz(before the change, it's ~68.5MHz).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 142b7222bbebe521d3f4b8d3850c40bd7660a7cf)
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 09b254cd4233..be7c0940c076 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -358,8 +358,8 @@ <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; |