diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2015-06-29 13:16:53 -0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2015-08-11 23:15:11 +0800 |
| commit | b6db3097db6bcd75061d0a0fdae1fbbcffc1bf2d (patch) | |
| tree | 03b00f9d01c1027f4d5509c815f84a55460abc72 /arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | |
| parent | d23dfefaf0b4b85756fa2bc90cae21c7d50043c4 (diff) | |
ARM: dts: imx6qdl-sabrelite: Allow HDMI and LVDS to work simultaneously
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Gary Bisson <gary.bisson@boundarydevices.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabrelite.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index fe010590fda2..2a39806b5aa2 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -166,6 +166,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; |