diff options
author | Sandor Yu <R01008@freescale.com> | 2015-09-21 17:34:34 +0800 |
---|---|---|
committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:01:36 -0600 |
commit | c15d2cd300e1ef5e5be369f7308090112fbfc367 (patch) | |
tree | af31cecc032c32a29ea76c77105e090712c92508 /arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |
parent | 9bd019f58541793e9e291bd464eb5e9b673f41de (diff) |
MLK-11508-5: dts: Add imx v4l2 capture driver
Add imx v4l2 capture driver.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 146 |
1 files changed, 122 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 5c4144236535..a9752bfa8aaa 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -97,6 +97,13 @@ startup-delay-us = <500>; enable-active-high; }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; + enable-active-high; + }; }; gpio-keys { @@ -219,15 +226,20 @@ status = "okay"; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; - red { - gpios = <&gpio1 2 0>; - default-state = "on"; - }; + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; }; v4l2_out { @@ -235,6 +247,12 @@ status = "okay"; }; + mipi_dsi_reset: mipi-dsi-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + #reset-cells = <0>; + }; }; &audmux { @@ -248,6 +266,11 @@ soc-supply = <&sw1c_reg>; }; +&clks { + fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; + fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>; @@ -276,6 +299,18 @@ fsl,ldo-bypass = <1>; }; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + &hdmi_audio { status = "okay"; }; @@ -337,6 +372,24 @@ interrupts = <18 8>; interrupt-route = <1>; }; + + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_2>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, + on rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c2 { @@ -345,12 +398,12 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - egalax_ts@04 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - interrupt-parent = <&gpio6>; - interrupts = <8 2>; - wakeup-gpios = <&gpio6 8 0>; + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ }; pmic: pfuze100@08 { @@ -456,6 +509,22 @@ compatible = "fsl,imx6-hdmi-i2c"; reg = <0x50>; }; + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 201>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c3 { @@ -499,22 +568,32 @@ imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 - MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 >; }; @@ -653,6 +732,8 @@ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 >; }; @@ -813,6 +894,23 @@ }; }; +&mipi_csi { + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + resets = <&mipi_dsi_reset>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; |