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authorRobby Cai <robby.cai@nxp.com>2019-09-27 20:59:56 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:08:02 +0800
commitb7ce0a73b2e6bb81eccfb965dac8143ed912df2a (patch)
treec7d95196aebfe7dfe934c2ed012fd58ec6a4afe5 /arch/arm/boot/dts/imx6qdl-sabresd.dtsi
parent76adf3e7d31c8c5450f7922fbdd253c131225295 (diff)
arm: dts: imx6qdl-sabresd: add V4L2 capture support
use internal version and resolve conflict with upstreaming code. add the nodes for v4l2 capture, mipi csi, and ov5460 cameras. Signed-off-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabresd.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi78
1 files changed, 78 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 1345f1552a67..19aa87dac527 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -228,6 +228,22 @@
default-state = "off";
};
};
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+ v4l2_cap_1 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
};
&ipu1_csi0_from_ipu1_csi0_mux {
@@ -238,7 +254,9 @@
};
&ipu1_csi0_mux_from_parallel_sensor {
+#if 0
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+#endif
};
&ipu1_csi0 {
@@ -249,6 +267,11 @@
&mipi_csi {
status = "okay";
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+#if 0
port@0 {
reg = <0>;
@@ -258,6 +281,7 @@
data-lanes = <1 2>;
};
};
+#endif
};
&audmux {
@@ -371,6 +395,7 @@
vddio-supply = <&reg_sensors>;
};
+#if 0
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
@@ -395,6 +420,23 @@
};
};
};
+#endif
+ ov564x: ov564x@3c {
+ compatible = "ovti,ov564x";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_2>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, on rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
+ rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ };
};
&i2c2 {
@@ -421,6 +463,7 @@
work-mode = <1>;/*DCM mode*/
};
+#if 0
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
@@ -443,6 +486,22 @@
};
};
};
+#endif
+
+ ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v rev C board is VGEN3 rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
+ rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ };
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
@@ -752,6 +811,25 @@
>;
};
+ pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ >;
+ };
+
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0