diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2017-04-12 18:45:59 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2017-05-15 09:34:28 +0800 |
| commit | e761b82ef22269b4e4fdf1a4d397c09522bc5d54 (patch) | |
| tree | 0435bef137ae1f5b8dfe88957ee2cd9a1d6db8aa /arch/arm/boot/dts/imx6qdl.dtsi | |
| parent | 1b1ec50366a87ed84ac07db9a09c56ac7cafb367 (diff) | |
ARM: dts: imx6: adopt DT to new GPC binding
Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 37 |
1 files changed, 26 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e426faa9c243..2c2af6737b0e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -156,7 +156,7 @@ <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; }; gpu_2d: gpu@00134000 { @@ -166,7 +166,7 @@ clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; }; timer@00a00600 { @@ -434,7 +434,7 @@ clocks = <&clks IMX6QDL_CLK_VPU_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; clock-names = "per", "ahb"; - power-domains = <&gpc 1>; + power-domains = <&pd_pu>; resets = <&src 1>; iram = <&ocram>; }; @@ -797,14 +797,29 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - #power-domain-cells = <1>; + clocks = <&clks IMX6QDL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + }; + }; }; gpr: iomuxc-gpr@020e0000 { |