diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2018-04-23 23:55:49 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:17 +0800 |
| commit | 95e6e2c6500c1c29e3c4d9b08bd9c909f86887e6 (patch) | |
| tree | 121ac7f972299d3f896850f973be887a787f2c38 /arch/arm/boot/dts/imx6sl.dtsi | |
| parent | 45f8c8d7741e5e067a5e40fbc6995cf27abcc141 (diff) | |
MGS-3705-1 gpu: dts: enable gpu devices for imx6
set GPU baseAddress with 256M on IMX6Q and iMX6QP,
add reserved cma in DTB to support different size,
the default cma size is 320M on all imx6 boards.
integrated patches from imx_4.9.y:
1.MGS-955 GPU:Integrate GPU module
commit: 73183c14a20d4f1d02317f80db3d90b3be1546fc
2.MGS-1211 gpu: add GPU for 6sl,6sx,6dl
commit: 80a8994c47cbb97fb31ef0efab92ddb29002448e
3.MGS-1087 gpu: Move the GPU reserved memory to DTS file
commit: ea0111da6892b52c790da607a3d91140d1ebf936
4.MGS-2540 [#ccc] Need set baseAddress with RAM start address on IMX6Q
commit: de838d99d9264884cbaaa601ab323a70b62634d9
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d72503ee91d7..a3355e579e7c 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -86,6 +86,20 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -1021,6 +1035,24 @@ reg = <0x021d8000 0x4000>; status = "disabled"; }; + + gpu: gpu@02200000 { + compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu"; + reg = <0x02200000 0x4000>, <0x02204000 0x4000>, + <0x80000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_2d", "iobase_vg", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_2d", "irq_vg"; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu2d_clk"; + resets = <&src 3>, <&src 3>; + reset-names = "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; }; }; }; |