MLK-13405-1 ARM: dts: add usdhc2 support for imx6sll-evk

For imx6sll-evk board, if eMMC connected, all the pad of
eMMC should be fixed to 1.8v. Otherwise the current leakage
will pull up the VCCQ to 2.6v, which will impatch usdhc1
and usdhc3 SD3.0 voltage switch.

This patch set the LVE of pad SD2_RST and SD2_STROBE, and
config the vqmmc to fixed 1.8v, make sure the driver set
pad I/O voltage of usdhc2 fixed to 1.8v, not impact the
VCCQ which support usdhc1 and usdhc3 SD3.0 1.8v voltage.

And accord to IC suggestion, clock and strobe pad need to
config as pull-down. So change all the clock/strobe pad's
PUS to 0.

eMMC data4/5 has branch on evk board, which make the data
signal quality very bad, need to cut off these branch of
data4/5, this hardware rework is hard to do on all the evk
board. So currently HS400 do not enable, just support eMMC
HS200 mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

1 files changed, 70 insertions, 22 deletions

diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
index cac27813996f..cc2f382627e0 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -95,11 +95,10 @@
 
 		reg_sd2_vmmc: sd2_vmmc {
 			compatible = "regulator-fixed";
-			regulator-name = "SD2_SPWR";
-			regulator-min-microvolt = <3000000>;
-			regulator-max-microvolt = <3000000>;
-			gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
+			regulator-name = "eMMC-VCCQ";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
 		};
 
 		reg_sd3_vmmc: sd3_vmmc {
@@ -361,7 +360,12 @@
 				MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
 				MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
 				MX6SLL_PAD_KEY_COL3__GPIO3_IO30	0x17059
-				MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x17059
+				/*
+				 * Must set the LVE of pad SD2_RESET, otherwise current
+				 * leakage through eMMC chip will pull high the VCCQ to
+				 * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
+				 */
+				MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
 				MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
 				MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
 				MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
@@ -514,7 +518,7 @@
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x17059
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13059
 				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
 				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
 				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
@@ -525,7 +529,7 @@
 		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
 			fsl,pins = <
 				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170b9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130b9
 				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
 				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
 				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
@@ -536,7 +540,7 @@
 		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
 			fsl,pins = <
 				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170f9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130f9
 				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
 				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
 				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
@@ -546,23 +550,56 @@
 
 		pinctrl_usdhc2: usdhc2grp {
 			fsl,pins = <
-				MX6SLL_PAD_SD2_CMD__SD2_CMD	0x17059
-				MX6SLL_PAD_SD2_CLK__SD2_CLK	0x17059
-				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
-				MX6SLL_PAD_SD2_DATA1__SD2_DATA1	0x17059
-				MX6SLL_PAD_SD2_DATA2__SD2_DATA2	0x17059
-				MX6SLL_PAD_SD2_DATA3__SD2_DATA3	0x17059
-				MX6SLL_PAD_SD2_DATA4__SD2_DATA4	0x17059
-				MX6SLL_PAD_SD2_DATA5__SD2_DATA5	0x17059
-				MX6SLL_PAD_SD2_DATA6__SD2_DATA6	0x17059
-				MX6SLL_PAD_SD2_DATA7__SD2_DATA7	0x17059
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x17059
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x17059
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x17059
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x17059
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x17059
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x413059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170b9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170b9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170b9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170b9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170b9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130b9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170f9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170f9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170f9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170f9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170f9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130f9
 			>;
 		};
 
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
 				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17059
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x17059
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x13059
 				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17059
 				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17059
 				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17059
@@ -573,7 +610,7 @@
 		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 			fsl,pins = <
 				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130b9
 				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
 				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
 				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
@@ -584,7 +621,7 @@
 		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 			fsl,pins = <
 				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130f9
 				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
 				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
 				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
@@ -692,6 +729,17 @@
 	status = "okay";
 };
 
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	vqmmc-supply = <&reg_sd2_vmmc>;
+	bus-width = <8>;
+	no-removable;
+	status = "okay";
+};
+
 &usdhc3 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;