diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2016-10-12 17:41:52 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:00 +0800 |
| commit | ae8382b08c55d982598eaca312976a112128dbdc (patch) | |
| tree | 3387d440308c74c9389d06fc1573b7409846ad40 /arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts | |
| parent | 87ab6f881ee30b0bc0e6cd14a26faf2baf3f8166 (diff) | |
MLK-13332-1 arm: dts: imx6sll-lpddr3-arm2: add SD3.0 support for SD1 slot
Add SD1 slot support for SD3.0 card.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts index fd53003ae6ae..d29b40a42130 100644 --- a/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts +++ b/arch/arm/boot/dts/imx6sll-lpddr3-arm2.dts @@ -223,6 +223,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 @@ -269,8 +291,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; keep-power-in-suspend; |