diff options
| author | Bai Ping <ping.bai@nxp.com> | 2016-10-14 13:11:29 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:07 +0800 |
| commit | 644e343400cadfe8353d755332b020f19a88e728 (patch) | |
| tree | 33d7e00c9023ca26de63c191b523341c28d5eb48 /arch/arm/boot/dts/imx6sll.dtsi | |
| parent | aaa50dd1700fc205a2338f966085b1e1a5c8cc52 (diff) | |
MLK-13344-02 ARM: dts: imx: update the setpoints on imx6sll
According to datasheet Rev.B,06/2016 of i.MX6SLL. It has below
setpoints support:
996MHz 1.2V
792MHz 1.15V
396MHz 1.05V
198MHz 0.95V
We add a 25mV margin to cover the IR drop and board tolerance.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 529d4c653616..604aed07974c 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -50,15 +50,17 @@ next-level-cache = <&L2>; operating-points = < /* kHz uV */ - 996000 1275000 + 996000 1225000 792000 1175000 - 396000 975000 + 396000 1075000 + 198000 975000 >; fsl,soc-operating-points = < /* ARM kHz SOC-PU uV */ 996000 1225000 792000 1175000 396000 1175000 + 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX6SLL_CLK_ARM>, |