diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-05-04 20:47:05 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:26 +0800 |
| commit | cd8bc8edd7fbdea60826347a7005ac8ee7831218 (patch) | |
| tree | b5e113237f88dca4d4feb62c4a9fcca86d06de2e /arch/arm/boot/dts/imx6sll.dtsi | |
| parent | b3db7efdc5bc616785adeac241fc094ea9348ef3 (diff) | |
arm: dts: imx: update the clocks of cpu node
Update the clocks of cpu to match with the
cpufreq driver.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll.dtsi | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index ca3b4304257b..40ce9a682c2d 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -65,13 +65,18 @@ >; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; + fsl,low-power-run; clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_PLL1_SW>, - <&clks IMX6SLL_CLK_PLL1_SYS>; + <&clks IMX6SLL_CLK_PLL1_SYS>, + <&clks IMX6SLL_CLK_PLL1>, + <&clks IMX6SLL_PLL1_BYPASS>, + <&clks IMX6SLL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; }; }; |