diff options
| author | Richard Zhu <Richard.Zhu@freescale.com> | 2015-09-14 15:47:23 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:17 +0800 |
| commit | 899789ae3fe9e13e0ee0f7a6633229dce40beec3 (patch) | |
| tree | fff6320cd494b1d6a3c9f26b4c1315ee32f749c8 /arch/arm/boot/dts/imx6sx.dtsi | |
| parent | a846c5adfcbff4ef581d1e707bd58e7d487541af (diff) | |
MLK-11561-1 ARM: imx: enable pcie on imx6sx platforms
enable pcie support on imx6sx platforms.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 35 |
1 files changed, 26 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 5db2168323c9..2de4ef6f98a4 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -690,9 +690,9 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie { + reg_pcie_phy: regulator-vddpcie-phy@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; + regulator-name = "vddpcie-phy"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; anatop-reg-offset = <0x140>; @@ -803,6 +803,15 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; + clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>, + <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix", + "lcdif_axi", "lcdif2_pix", "csi_mclk"; + pcie-phy-supply = <®_pcie_phy>; + #power-domain-cells = <1>; }; iomuxc: iomuxc@020e0000 { @@ -1379,12 +1388,12 @@ pcie: pcie@8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 + ranges = < /* downstream I/O */ 0x81000000 0 0 0x08f80000 0 0x00010000 /* non-prefetchable memory */ @@ -1392,12 +1401,20 @@ bus-range = <0x00 0xff>; num-lanes = <1>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + pcie-phy-supply = <®_pcie_phy>; + power-domains = <&gpc 2>; status = "disabled"; }; }; |