diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-04-18 15:55:54 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:11 +0800 |
| commit | cf6f49c0243c4ac1628b46f2d1b45c7287b70e7f (patch) | |
| tree | 88b8fae8e903c0bb5dddab09c46a521941b51186 /arch/arm/boot/dts/imx6sx.dtsi | |
| parent | dfa9c3b870b5d024b38f20b48d6892114fdb5799 (diff) | |
ARM: dts: imx6sx: add more clocks for cpu-freq driver
When cpu-freq driver switch ARM clock source from PLL1 to
STEP clock, need to keep PLL1 enabled and from its bypass
clock source OSC, this is necessary for i.MX6SX low power
idle.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index ae66b4940396..1bdc964e79c8 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -82,9 +82,13 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; |