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authorFugang Duan <fugang.duan@nxp.com>2020-02-21 12:53:31 +0800
committerFugang Duan <fugang.duan@nxp.com>2020-02-24 14:25:35 +0800
commitbd033629a7aef48d999fca7dea1b164598d37de8 (patch)
treef67f73f75f921ed1a7cbf45a1cc5422415bbe24d /arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
parente11246aa8f332d606d6a936ecfdcce1249402c97 (diff)
LF-982 arm: dts: imx6ul: add uart2 DTE pin group
Add uart2 DTE pin group for DTE test. Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul-14x14-evk.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6ul-14x14-evk.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index f49f500c19ef..9c8e1c938340 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -391,6 +391,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
+ /* for DTE mode, add below change */
+ /* fsl,dte-mode; */
+ /* pinctrl-0 = <&pinctrl_uart2dte>; */
status = "okay";
};
@@ -631,6 +634,15 @@
>;
};
+ pinctrl_uart2dte: uart2dtegrp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
+ >;
+ };
+
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059