diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-04-30 17:59:06 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:22:50 -0500 |
| commit | 34a7358e46ab6a1f38cddc706ef66c8d53e8f02c (patch) | |
| tree | e47859360708659b7d01c341927717137d486c36 /arch/arm/boot/dts/imx6ul-pinfunc.h | |
| parent | 6b484210e8ecb523bb9a76bca3b86ab2d27a2d4f (diff) | |
MLK-10792 ARM: dts: imx6ul: enable gpio-spi 74LV595PW support
Enable gpio-spi 74LV595PW support.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul-pinfunc.h')
| -rwxr-xr-x | arch/arm/boot/dts/imx6ul-pinfunc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h index c6d8c7c64e00..cae3ff7d5ab5 100755 --- a/arch/arm/boot/dts/imx6ul-pinfunc.h +++ b/arch/arm/boot/dts/imx6ul-pinfunc.h @@ -14,9 +14,20 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02A0 0x0000 5 0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02A4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001C 0x02A8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02AC 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02B0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02B4 0x0000 5 0 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002C 0x02B8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02BC 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02C0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02C4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003C 0x02C8 0x0000 5 0 #define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02CC 0x0000 5 0 + #define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02D0 0x0000 0 0 #define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02D0 0x05A0 1 0 #define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02D0 0x0000 2 0 |