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authorHaibo Chen <haibo.chen@nxp.com>2016-09-06 13:19:37 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:24:56 +0800
commit95bdbbee3b81b228f9708289f1acb6a5737c568c (patch)
tree9ac9c171140fba5af327ea4b916ba5a5ad385479 /arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
parentc093b2c2cc676d67112fc572dd89b650ff8ef10b (diff)
MLK-13188-2 dts: imx6ull: change the usdhc root clock to 396MHz
Due to the errata ERR010450 limit, this patch change the imx6ull usdhc root clock to 132MHz in soc related dts file, remove all the root clock setting in board dts file, after this patch, SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts')
-rw-r--r--arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
index 69323b663a50..934e6f6b8502 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts
@@ -12,9 +12,6 @@
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
- assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>;
- assigned-clock-rates = <0>, <176000000>;
cd-gpios = <>;
wp-gpios = <>;
vmmc-supply = <>;