diff options
| author | Bai Ping <ping.bai@nxp.com> | 2016-05-16 14:01:06 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:24:43 +0800 |
| commit | 5166c54ce215257afed84beb076471544224da65 (patch) | |
| tree | 4f2f94a0b9240bfc2bd706beef5ce430dd0b2f53 /arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts | |
| parent | dea3455ad7e7acfe8019836931402b1e810135a7 (diff) | |
MLK-12796-02 ARM: dts: imx: Add additional pinfunc define for imx6ull
On i.MX6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins have been move to the IOMUXC_SNVS. Add additional pinfunc define
and correct the pinctrl binding.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts index cfbcc11c7644..fcd1c84df16f 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts @@ -402,13 +402,6 @@ >; }; - pinctrl_bt: btgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 - >; - }; pinctrl_csi1: csi1grp { fsl,pins = < @@ -656,7 +649,6 @@ MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 >; }; @@ -852,6 +844,24 @@ }; }; +&iomuxc_snvs { + imx6ul-ddr3-arm2 { + pinctrl_bt: btgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + }; +}; + &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat |